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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-13 16:51:45 -0800 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-15 14:02:40 -0800 |
| commit | 9f93b98c87cfdbcbeb59b9da298344c840f747a4 (patch) | |
| tree | 3ba6d247ca03596c7a9b9ab7ed93957a69b33c6d /riscv/mmu.cc | |
| parent | 4d4159e76d61980e300cea7bdbdab873f07db12a (diff) | |
| download | riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.zip riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.gz riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.bz2 | |
Rename memif_endianness_t to endianness_t
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 1d15b91..fa873d9 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -5,10 +5,10 @@ #include "simif.h" #include "processor.h" -mmu_t::mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc) +mmu_t::mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc) : sim(sim), proc(proc), #ifdef RISCV_ENABLE_DUAL_ENDIAN - target_big_endian(endianness == memif_endianness_big), + target_big_endian(endianness == endianness_big), #endif check_triggers_fetch(false), check_triggers_load(false), @@ -16,7 +16,7 @@ mmu_t::mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc) matched_trigger(NULL) { #ifndef RISCV_ENABLE_DUAL_ENDIAN - assert(endianness == memif_endianness_little); + assert(endianness == endianness_little); #endif flush_tlb(); yield_load_reservation(); |