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author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-13 16:51:45 -0800 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-15 14:02:40 -0800 |
commit | 9f93b98c87cfdbcbeb59b9da298344c840f747a4 (patch) | |
tree | 3ba6d247ca03596c7a9b9ab7ed93957a69b33c6d | |
parent | 4d4159e76d61980e300cea7bdbdab873f07db12a (diff) | |
download | riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.zip riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.gz riscv-isa-sim-9f93b98c87cfdbcbeb59b9da298344c840f747a4.tar.bz2 |
Rename memif_endianness_t to endianness_t
-rw-r--r-- | fesvr/elfloader.cc | 4 | ||||
-rw-r--r-- | fesvr/htif.h | 12 | ||||
-rw-r--r-- | fesvr/memif.h | 6 | ||||
-rw-r--r-- | riscv/cfg.h | 10 | ||||
-rw-r--r-- | riscv/mmu.cc | 6 | ||||
-rw-r--r-- | riscv/mmu.h | 2 | ||||
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/processor.h | 2 | ||||
-rw-r--r-- | riscv/sim.cc | 8 | ||||
-rw-r--r-- | riscv/sim.h | 2 | ||||
-rw-r--r-- | spike_main/spike-log-parser.cc | 2 | ||||
-rw-r--r-- | spike_main/spike.cc | 4 |
12 files changed, 30 insertions, 30 deletions
diff --git a/fesvr/elfloader.cc b/fesvr/elfloader.cc index 7357b47..192de65 100644 --- a/fesvr/elfloader.cc +++ b/fesvr/elfloader.cc @@ -98,7 +98,7 @@ std::map<std::string, uint64_t> load_elf(const char* fn, memif_t* memif, reg_t* } while (0) if (IS_ELFLE(*eh64)) { - if (memif->get_target_endianness() != memif_endianness_little) { + if (memif->get_target_endianness() != endianness_little) { throw std::invalid_argument("Specified ELF is little endian, but system uses a big-endian memory system. Rerun without --big-endian"); } if (IS_ELF32(*eh64)) @@ -109,7 +109,7 @@ std::map<std::string, uint64_t> load_elf(const char* fn, memif_t* memif, reg_t* #ifndef RISCV_ENABLE_DUAL_ENDIAN throw std::invalid_argument("Specified ELF is big endian. Configure with --enable-dual-endian to enable support"); #else - if (memif->get_target_endianness() != memif_endianness_big) { + if (memif->get_target_endianness() != endianness_big) { throw std::invalid_argument("Specified ELF is big endian, but system uses a little-endian memory system. Rerun with --big-endian"); } if (IS_ELF32(*eh64)) diff --git a/fesvr/htif.h b/fesvr/htif.h index 5767e31..f63ff1c 100644 --- a/fesvr/htif.h +++ b/fesvr/htif.h @@ -31,18 +31,18 @@ class htif_t : public chunked_memif_t template<typename T> inline T from_target(target_endian<T> n) const { - memif_endianness_t endianness = get_target_endianness(); - assert(endianness == memif_endianness_little || endianness == memif_endianness_big); + endianness_t endianness = get_target_endianness(); + assert(endianness == endianness_little || endianness == endianness_big); - return endianness == memif_endianness_big? n.from_be() : n.from_le(); + return endianness == endianness_big? n.from_be() : n.from_le(); } template<typename T> inline target_endian<T> to_target(T n) const { - memif_endianness_t endianness = get_target_endianness(); - assert(endianness == memif_endianness_little || endianness == memif_endianness_big); + endianness_t endianness = get_target_endianness(); + assert(endianness == endianness_little || endianness == endianness_big); - return endianness == memif_endianness_big? target_endian<T>::to_be(n) : target_endian<T>::to_le(n); + return endianness == endianness_big? target_endian<T>::to_be(n) : target_endian<T>::to_le(n); } protected: diff --git a/fesvr/memif.h b/fesvr/memif.h index aa4ca98..fff2f55 100644 --- a/fesvr/memif.h +++ b/fesvr/memif.h @@ -23,8 +23,8 @@ public: virtual size_t chunk_align() = 0; virtual size_t chunk_max_size() = 0; - virtual memif_endianness_t get_target_endianness() const { - return memif_endianness_little; + virtual endianness_t get_target_endianness() const { + return endianness_little; } virtual ~chunked_memif_t() = default; @@ -65,7 +65,7 @@ public: virtual void write_int64(addr_t addr, target_endian<int64_t> val); // endianness - virtual memif_endianness_t get_target_endianness() const { + virtual endianness_t get_target_endianness() const { return cmemif->get_target_endianness(); } diff --git a/riscv/cfg.h b/riscv/cfg.h index 1ca7c77..cd99828 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -7,9 +7,9 @@ #include <cassert> typedef enum { - memif_endianness_little, - memif_endianness_big -} memif_endianness_t; + endianness_little, + endianness_big +} endianness_t; template <typename T> class cfg_arg_t { @@ -51,7 +51,7 @@ public: const char *default_bootargs, const char *default_isa, const char *default_priv, const char *default_varch, - const memif_endianness_t default_endianness, + const endianness_t default_endianness, const reg_t default_pmpregions, const std::vector<mem_cfg_t> &default_mem_layout, const std::vector<int> default_hartids, @@ -74,7 +74,7 @@ public: cfg_arg_t<const char *> isa; cfg_arg_t<const char *> priv; cfg_arg_t<const char *> varch; - memif_endianness_t endianness; + endianness_t endianness; reg_t pmpregions; cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; std::optional<reg_t> start_pc; diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 1d15b91..fa873d9 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -5,10 +5,10 @@ #include "simif.h" #include "processor.h" -mmu_t::mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc) +mmu_t::mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc) : sim(sim), proc(proc), #ifdef RISCV_ENABLE_DUAL_ENDIAN - target_big_endian(endianness == memif_endianness_big), + target_big_endian(endianness == endianness_big), #endif check_triggers_fetch(false), check_triggers_load(false), @@ -16,7 +16,7 @@ mmu_t::mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc) matched_trigger(NULL) { #ifndef RISCV_ENABLE_DUAL_ENDIAN - assert(endianness == memif_endianness_little); + assert(endianness == endianness_little); #endif flush_tlb(); yield_load_reservation(); diff --git a/riscv/mmu.h b/riscv/mmu.h index 5d92a9e..3e5863d 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -47,7 +47,7 @@ private: std::map<reg_t, reg_t> alloc_cache; std::vector<std::pair<reg_t, reg_t >> addr_tbl; public: - mmu_t(simif_t* sim, memif_endianness_t endianness, processor_t* proc); + mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc); ~mmu_t(); #define RISCV_XLATE_VIRT (1U << 0) diff --git a/riscv/processor.cc b/riscv/processor.cc index 8ca3bb7..560f71e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -30,7 +30,7 @@ processor_t::processor_t(const isa_parser_t *isa, const char* varch, simif_t* sim, uint32_t id, bool halt_on_reset, - memif_endianness_t endianness, + endianness_t endianness, FILE* log_file, std::ostream& sout_) : debug(false), halt_request(HR_NONE), isa(isa), sim(sim), id(id), xlen(0), histogram_enabled(false), log_commits_enabled(false), diff --git a/riscv/processor.h b/riscv/processor.h index 4153cfd..c2da56d 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -170,7 +170,7 @@ class processor_t : public abstract_device_t public: processor_t(const isa_parser_t *isa, const char* varch, simif_t* sim, uint32_t id, bool halt_on_reset, - memif_endianness_t endianness, + endianness_t endianness, FILE *log_file, std::ostream& sout_); // because of command line option --log and -s we need both ~processor_t(); diff --git a/riscv/sim.cc b/riscv/sim.cc index 8a65797..361008b 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -86,7 +86,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, #endif #ifndef RISCV_ENABLE_DUAL_ENDIAN - if (cfg->endianness != memif_endianness_little) { + if (cfg->endianness != endianness_little) { fputs("Big-endian support has not been prroperly enabled; " "please rebuild the riscv-isa-sim project using " "\"configure --enable-dual-endian\".\n", @@ -375,7 +375,7 @@ void sim_t::set_rom() (uint32_t) (start_pc & 0xffffffff), (uint32_t) (start_pc >> 32) }; - if (get_target_endianness() == memif_endianness_big) { + if (get_target_endianness() == endianness_big) { int i; // Instuctions are little endian for (i = 0; reset_vec[i] != 0; i++) @@ -445,9 +445,9 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) debug_mmu->store<uint64_t>(taddr, debug_mmu->from_target(data)); } -memif_endianness_t sim_t::get_target_endianness() const +endianness_t sim_t::get_target_endianness() const { - return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little; + return debug_mmu->is_target_big_endian()? endianness_big : endianness_little; } void sim_t::proc_reset(unsigned id) diff --git a/riscv/sim.h b/riscv/sim.h index b3b5d40..cc0c48c 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -151,7 +151,7 @@ private: void write_chunk(addr_t taddr, size_t len, const void* src); size_t chunk_align() { return 8; } size_t chunk_max_size() { return 8; } - memif_endianness_t get_target_endianness() const; + endianness_t get_target_endianness() const; public: // Initialize this after procs, because in debug_module_t::reset() we diff --git a/spike_main/spike-log-parser.cc b/spike_main/spike-log-parser.cc index efe6955..e5511e5 100644 --- a/spike_main/spike-log-parser.cc +++ b/spike_main/spike-log-parser.cc @@ -28,7 +28,7 @@ int main(int UNUSED argc, char** argv) parser.parse(argv); isa_parser_t isa(isa_string, DEFAULT_PRIV); - processor_t p(&isa, DEFAULT_VARCH, 0, 0, false, memif_endianness_little, nullptr, cerr); + processor_t p(&isa, DEFAULT_VARCH, 0, 0, false, endianness_little, nullptr, cerr); if (extension) { p.register_extension(extension()); } diff --git a/spike_main/spike.cc b/spike_main/spike.cc index f0d6920..f183e5b 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -326,7 +326,7 @@ int main(int argc, char** argv) /*default_isa=*/DEFAULT_ISA, /*default_priv=*/DEFAULT_PRIV, /*default_varch=*/DEFAULT_VARCH, - /*default_endianness*/memif_endianness_little, + /*default_endianness*/endianness_little, /*default_pmpregions=*/16, /*default_mem_layout=*/parse_mem_layout("2048"), /*default_hartids=*/std::vector<int>(), @@ -397,7 +397,7 @@ int main(int argc, char** argv) parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));}); parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));}); parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));}); - parser.option(0, "big-endian", 0, [&](const char UNUSED *s){cfg.endianness = memif_endianness_big;}); + parser.option(0, "big-endian", 0, [&](const char UNUSED *s){cfg.endianness = endianness_big;}); parser.option(0, "log-cache-miss", 0, [&](const char UNUSED *s){log_cache = true;}); parser.option(0, "isa", 1, [&](const char* s){cfg.isa = s;}); parser.option(0, "pmpregions", 1, [&](const char* s){cfg.pmpregions = atoul_safe(s);}); |