Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-05-19 | fdt: import fdt library from OpenSBI | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-14 | rvv: add vzext/vsext | Chih-Min Chao | 1 | -0/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-13 | rvv: change to 0.9amo | Chih-Min Chao | 1 | -9/+36 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-13 | rvv: amo pre-0.9 | Chih-Min Chao | 1 | -0/+12 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-11 | rvv: change to 0.9 ldst | Chih-Min Chao | 1 | -44/+32 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-04 | zfh: implementation all instructions | Chih-Min Chao | 1 | -0/+39 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-04-14 | rvv: add vfslide1[down|up].vf and refine checking rule | Chih-Min Chao | 1 | -0/+2 | |
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-04-14 | rvv: add float conversion for rtz variants | Chih-Min Chao | 1 | -0/+6 | |
new features in spec 0.9 ref: https://github.com/riscv/riscv-v-spec/issues/352 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-01-06 | rvv : vmv[1248]r.v | Chih-Min Chao | 1 | -0/+4 | |
simple register copy instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: add whole register load/store, vl1r.v/vs1r.v | Chih-Min Chao | 1 | -0/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: add unsigned average | Chih-Min Chao | 1 | -0/+4 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: replace vn suffic by 'w' | Chih-Min Chao | 1 | -12/+12 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: rename vfncvt suffix and add rod rouding type | Chih-Min Chao | 1 | -5/+6 | |
1. vfncvt*.v -> vfncvt*.w 2. add vfncvt.rod.f.f.w Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: add vqm* 'Quad-Widening Integer Multiply-Add' | Chih-Min Chao | 1 | -0/+7 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-27 | rvv: add quad insn and new vlenb csr | Chih-Min Chao | 1 | -7/+0 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-17 | Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu | Andrew Waterman | 1 | -1/+0 | |
2019-10-22 | rvv: remove vmford | Chih-Min Chao | 1 | -2/+0 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-09-05 | rvv: change vext to vmv | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-09-05 | Revert "vext.x.v -> vmv.x.s; unary operation encoding changes" | Chih-Min Chao | 1 | -1/+1 | |
This reverts commit f36b73e4741e42bf5786cbac0bf022f1e9bfe309. to makeh 0.7.2-0616-draft | |||||
2019-09-04 | Implement MMIO device plugins. | Aaron Jones | 1 | -0/+3 | |
2019-09-04 | vext.x.v -> vmv.x.s; unary operation encoding changes | Andrew Waterman | 1 | -1/+1 | |
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085 | |||||
2019-09-04 | vmfirst/vmpopc have been renamed to vfirst/vpopc | Andrew Waterman | 1 | -2/+2 | |
2019-07-22 | Remove old header from makefile | Andrew Waterman | 1 | -1/+0 | |
Resolves #308 | |||||
2019-07-22 | Fix support for 32-bit hosts (but no V extension in that case!) | Andrew Waterman | 1 | -1/+1 | |
2019-06-14 | rvv: sort instruction list | Chih-Min Chao | 1 | -16/+16 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-13 | rvv: separte vfunary0 into independent instructions | Chih-Min Chao | 1 | -1/+14 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-13 | rvv: spearate vfunary1 into independent instructions | Chih-Min Chao | 1 | -1/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-10 | rvv: fix vfw[add|sub].w[vf] | Chih-Min Chao | 1 | -2/+3 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-10 | rvv: fix widen fpu zero and function | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-09 | rvv: add missing targets vfwadd_vf and vfwadd_wf | Dave.Wen | 1 | -0/+2 | |
2019-06-06 | rvv: follow new instruction name change | Chih-Min Chao | 1 | -20/+18 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: sepapate vfmerge | Chih-Min Chao | 1 | -1/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: add new adc/sbc | Chih-Min Chao | 1 | -0/+5 | |
change vadc.v[vix] -> vadc.v[vix]m add vmadc.v[vix]m change vsbc.v[vx] -> vsbc.v[vx]m add vmsbc.v[vx]m Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]m | Chih-Min Chao | 1 | -5/+5 | |
also add vmsdc/vmadc encoding/disasm Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: separate vmerge and vmv | Chih-Min Chao | 1 | -3/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: vmiota_m -> viota_m | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: change vseq.?? to vmseq.?? and related insns | Chih-Min Chao | 1 | -20/+20 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: add vfrsub.vf | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-04 | rvv: change vfeq to vmfeq and related comparision instruction | Chih-Min Chao | 1 | -12/+12 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-20 | rvv: change viota_m to vmiota_m | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-19 | rvv: separate vmuary0 by new encoding change | Chih-Min Chao | 1 | -1/+5 | |
follow riscv-opcode 7ebe3a7 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-16 | rvv: fix missng empty line | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-16 | rvv: fix integer reduction instruction suffix | Chih-Min Chao | 1 | -9/+8 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-13 | Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 ↵ | Chih-Min Chao | 1 | -2/+0 | |
in registers" this is experimental implementation This reverts commit f04f29d352d413d2bc1ed1c7f60319461746540a. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-13 | rvv: makefile spearate instruction for differenct extension | Chih-Min Chao | 1 | -381/+422 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-10 | rvv: add unordred indexed store | Chih-Min Chao | 1 | -0/+4 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-06 | rvv: add vwredsum | Chih-Min Chao | 1 | -0/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-02 | rvv: add vmunary0_vv | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-01 | rvv: add fault-first only load | Chih-Min Chao | 1 | -0/+7 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-01 | rvv: add element load/store | Chih-Min Chao | 1 | -0/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> |