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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 19:44:13 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 19:47:39 -0700 |
| commit | e60e0c8006bacc24eedeb786a8b493d50c425e2f (patch) | |
| tree | f671249e6dafb8652cbcc5080810cd5a48a61ad5 /riscv/riscv.mk.in | |
| parent | 3ced1dc5a10a6e99130e4483de6ffbab498a57e8 (diff) | |
| download | spike-e60e0c8006bacc24eedeb786a8b493d50c425e2f.zip spike-e60e0c8006bacc24eedeb786a8b493d50c425e2f.tar.gz spike-e60e0c8006bacc24eedeb786a8b493d50c425e2f.tar.bz2 | |
Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers"
this is experimental implementation
This reverts commit f04f29d352d413d2bc1ed1c7f60319461746540a.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 1455ccd..65b1288 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -643,8 +643,6 @@ riscv_insn_list = \ $(riscv_insn_ext_q) \ $(riscv_insn_ext_v) \ $(riscv_insn_priv) \ - flh \ - fsh \ riscv_gen_srcs = \ $(addsuffix .cc,$(riscv_insn_list)) |