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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-18 20:19:36 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-27 19:50:20 -0800 |
| commit | 7364212af9578ea65ddea35a6992bdc8e4efd675 (patch) | |
| tree | 3c3fbcf4517abbc720b136b9cf593eb7cffd05a1 /riscv/riscv.mk.in | |
| parent | 63197a1f330aae5775090d6ce65ab3fab436e4e9 (diff) | |
| download | spike-7364212af9578ea65ddea35a6992bdc8e4efd675.zip spike-7364212af9578ea65ddea35a6992bdc8e4efd675.tar.gz spike-7364212af9578ea65ddea35a6992bdc8e4efd675.tar.bz2 | |
rvv: add quad insn and new vlenb csr
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index a1fc513..1e7764d 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -478,13 +478,6 @@ riscv_insn_ext_v_alu_int = \ vwmulu_vx \ vwredsum_vs \ vwredsumu_vs \ - vwsmacc_vv \ - vwsmacc_vx \ - vwsmaccsu_vv \ - vwsmaccsu_vx \ - vwsmaccu_vv \ - vwsmaccu_vx \ - vwsmaccus_vx \ vwsub_vv \ vwsub_vx \ vwsub_wv \ |