aboutsummaryrefslogtreecommitdiff
path: root/drivers/pci
AgeCommit message (Collapse)AuthorFilesLines
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass20-0/+20
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-27pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more)Stefan Roese2-81/+41
This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27arm64: a37xx: pci: Fix printing debug messagesPali Rohár1-3/+2
Value pcie->dev in function pcie_advk_probe() is not initialized yet so use dev as argument for dev_dbg()/dev_warn(). Function pcie_advk_wait_pio() itself prints error message on failure so do not print duplicate error message in caller. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27pci: pci_mvebu: Define an IO region as wellPhil Sutter1-1/+27
Configure an IO region and window for PNP identical to how MEM region is set up. Linux does this only if the DT defines a pcie-io-aperture property for the SOC, but since all supported boards do this should not be needed. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27pci: Make auto-config code a little more robustPhil Sutter1-4/+5
On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-21pci: Add Rockchip dwc based PCIe controller driverShawn Lin3-0/+887
Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-15common: board_r: Drop initr_pci wrapperOvidiu Panait2-3/+7
Add a return value to pci_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-05Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2-10/+10
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-05Merge tag 'v2021.01-rc5' into nextTom Rini6-16/+41
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass1-3/+3
We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05dm: core: Rename sqq to seq_Simon Glass1-1/+1
Now that the sequence-numbering migration is complete, rename this member back to seq_, adding an underscore to indicate it is internal to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass2-6/+6
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-28Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"Pali Rohár1-3/+0
This reverts commit 828d32621686aec593076d16445d39b9b8d49c05. This change revers code which asserting PERST# signal when unloading driver. Driver's remove callback is still there as it is used for other functionality. Asserting PERST# signal prior booting kernel is causing that A3720 boards (Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and 4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900) and anymore. When PERST# signal is not asserted these cards are detected correctly. As this is regression for existing stable Linux kernel versions revert this problematic change in U-Boot. To make cards working with OpenWRT 4.14 kernel it is needed to disable link training prior booting kernel, which is already done in driver's remove callback. Described issue is in Linux kernel pci aardvark driver which is (hopefully) fixed in latest upstream versions. Latest upstream versions should be able to initialize PCIe bus and detects cards independently of the link training and PERST# signal state. So with this change, U-Boot on A3720 boards should be able to boot OpenWRT 4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-12-18dm: core: Update uclass_find_next_free_req_seq() for new schemeSimon Glass1-1/+1
This function current deals with req_seq which is deprecated. Update it to use the new sequence numbers, putting them above existing aliases. Rename the function to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18pci: Update to use new sequence numbersSimon Glass2-23/+32
Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18dm: Avoid accessing seq directlySimon Glass14-56/+56
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass5-20/+20
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Update 'auto' declarations to be on one lineSimon Glass2-4/+2
Fix up the code style for those declarations that should now fit onto one line, which is all of them that currently do not. This is needed for dtoc to detect the structs correctly, at present. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass17-39/+39
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2-12/+12
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass7-21/+21
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass25-30/+30
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind_ofnode() to device_bind()Simon Glass2-4/+4
This is the standard function to use when binding devices. Drop the '_ofnode' suffix to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-10pci: layerscape: fix a dead loop issueHou Zhiqiang1-0/+2
Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Fixed checkpatch error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal3-5/+10
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: ls_pcie_g4: Add size check for config resourceWasim Khan1-0/+8
resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: layerscape: Add size check for config resourceWasim Khan1-1/+7
resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: ls_pcie_g4: Print pcie controller number starting from 1Wasim Khan1-4/+7
Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
2020-12-10pci: layerscape: Update print of pcie controllerWasim Khan2-3/+7
Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Trimmed subject] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23dm: pci: fsl: Correct the workaround of erratum A-007815Hou Zhiqiang2-4/+18
The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2-0/+340
In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: move pci node search in a common functionLaurentiu Tudor1-42/+34
Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: move per-pci device fdt fixup in a functionLaurentiu Tudor1-26/+34
Move the pci device related fdt fixup in a function in order to re-use it in a following patch. While at it, improve the error handling. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-05Merge branch 'next'Tom Rini1-1/+2
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2-0/+32
- Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on layerscape products
2020-09-24pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2Hou Zhiqiang1-0/+26
LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24arm64: a37xx: pci: Disable link training when unloading driverPali Rohár1-0/+5
As required by PCI Express spec a delay for at least 100ms after de-asserting PERST# signal is needed before link training is enabled. Linux kernels prior to 5.8 version do not automatically disable link training before de-asserting PERST# signal, therefore this requirement is not fulfilled. Above requirement is needed for proper detection of some Compex PCIe WiFi cards. Otherwise Linux kernel cannot detect it. To allow using those PCIe cards with older Linux kernel versions booted by U-Boot compiled with U-Boot a37xx pci driver, disable link training in U-Boot when unloading this pci driver. Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver when booting Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-23pci: layerscape: Fix spurious writes and panicMichael Walle1-0/+6
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI root devices are layerscape PCIe controllers. Unfortunately, this is not true for the LS1028A. There is one additional static PCI root complex (this contains the networking devices) which has nothing to do with the layerscape PCIe controllers. On recent U-Boot versions this results in the following panic: "Synchronous Abort" handler, esr 0x96000044 elr: 000000009602fa04 lr : 000000009602f9f4 (reloc) elr: 00000000fbd73a04 lr : 00000000fbd739f4 x0 : 0080000002000101 x1 : 0000000000000000 x2 : 00000000fbde9000 x3 : 0000000000000001 x4 : 0000000000000000 x5 : 0000000000000030 x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0 x8 : 0000000000000002 x9 : 000000000000000c x10: 00000000ffffffe8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000000a2c x14: 00000000fbb3d2cc x15: 00000000ffffffff x16: 0000000000010000 x17: 0000000000000000 x18: 00000000fbb3fda0 x19: 0000000000000800 x20: 0000000000000000 x21: 00000001f0000000 x22: 0000000000000800 x23: 0000000000000009 x24: 00000000fbdc3c1b x25: 00000000fbdc28e5 x26: 00000000fbdcc008 x27: 00000000fbdc16e2 x28: 000000000f000000 x29: 00000000fbb3d3a0 Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814) Resetting CPU ... This bug already existed in former versions, but the spurious write was never trapped, because the destination address was a valid address (by pure luck). Make sure the PCI root is actually one of the expected PCIe layerscape controllers by matching its compatible string. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-10PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu1-6/+13
On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu1-6/+13
On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-07Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of ↵Tom Rini1-1/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
2020-08-31arm64: a37xx: pci: Depends on DM_GPIOPali Rohár2-8/+3
For proper initialization of aardvark pci driver it is required to de-assert reset GPIO. So depeneds on DM_GPIO option. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Assert PERST# signal when unloading driverPali Rohár1-6/+21
This change ensures that PCIe card is put into reset state when U-Boot stops using it. DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback prior booting Linux kernel. Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal prior initializing it. If it does not issue reset then some PCIe cards (specially Compex WiFi cards) are not detected at all. Putting PCIe card into reset state prior booting Linux kernel would ensure that card would be properly reset at time when Linux kernel starts initializing pci-aardvark driver. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DTPali Rohár1-3/+3
Change active-high to active-low and change DT property name from reset-gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver in Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-27pci: kconfig: Setup proper dependency for PCIE_ROCKCHIPMichal Simek1-0/+1
There is missing dependency for PCIE_ROCKCHIP which selects PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP. WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE Depends on [n]: ARCH_ROCKCHIP [=n] Selected by [y]: - PCIE_ROCKCHIP [=y] && PCI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-26CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always definedStefan Roese1-1/+2
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") & commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"), CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default). It makes no sense to still carry code that is guarded with "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes all these unreferenced code paths. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: Add PCI controller driver for OcteonTX / TX2Suneel Garapati3-0/+373
Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Check validity of ofnodeSuneel Garapati1-3/+7
Add check if the referenced ofnode is valid. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Alternate-RoutingID capabilitySuneel Garapati2-0/+35
If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add VF BAR map support for Enhanced AllocationSuneel Garapati1-5/+62
Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-09-03 07:59:06 +0000