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| author | Wasim Khan <wasim.khan@nxp.com> | 2020-09-28 16:26:05 +0530 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-12-10 13:56:38 +0530 |
| commit | eac364416c62ea1f49934f762e184616a04adede (patch) | |
| tree | 631cc5c1970d070780625e3e08cdd478805409bf /drivers/pci | |
| parent | b6c6a245bfe0c7d76fa5bb6d079ef5b85e14e835 (diff) | |
| download | u-boot-eac364416c62ea1f49934f762e184616a04adede.zip u-boot-eac364416c62ea1f49934f762e184616a04adede.tar.gz u-boot-eac364416c62ea1f49934f762e184616a04adede.tar.bz2 | |
pci: ls_pcie_g4: Print pcie controller number starting from 1
Print pcie controller number starting from 1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie_layerscape_gen4.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 428bfca..0226bde 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * * PCIe Gen4 driver for NXP Layerscape SoCs * Author: Hou Zhiqiang <Minder.Hou@gmail.com> @@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); if (!pcie->enabled) { - printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx), + dev->name); return 0; } @@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev) pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f; if (pcie->mode == PCI_HEADER_TYPE_NORMAL) { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Endpoint"); ls_pcie_g4_setup_ep(pcie); } else { - printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); + printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, + "Root Complex"); ls_pcie_g4_setup_ctrl(pcie); } |