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| author | Wasim Khan <wasim.khan@nxp.com> | 2020-09-28 16:26:13 +0530 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-12-10 13:56:39 +0530 |
| commit | 49df7c90867c0a991222f6a4eac8e42879880c23 (patch) | |
| tree | 0c4668b81b12965b81f5bad7f76ba17886f34428 /drivers/pci | |
| parent | 4c72d2d53bfcbf8003ba715ab3a3bac8cbf50b21 (diff) | |
| download | u-boot-49df7c90867c0a991222f6a4eac8e42879880c23.zip u-boot-49df7c90867c0a991222f6a4eac8e42879880c23.tar.gz u-boot-49df7c90867c0a991222f6a4eac8e42879880c23.tar.bz2 | |
pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space
as per hardware documentation.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie_layerscape_rc.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index f9e3089..cdfcad6 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev) return ret; } + cfg_size = fdt_resource_size(&pcie_rc->cfg_res); + if (cfg_size < SZ_8K) { + printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n", + PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K); + return 0; + } + /* * Fix the pcie memory map address and PF control registers address * for LS2088A series SoCs @@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev) if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || svr == SVR_LS2081A || svr == SVR_LS2041A) { - cfg_size = fdt_resource_size(&pcie_rc->cfg_res); pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size; |