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14 daysMerge tag 'v2024.07-rc5' into nextTom Rini3-0/+176
Prepare v2024.07-rc5
2024-06-17mtd: spi-nor: Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash partPrasad Kummari1-1/+1
Added SPI_NOR_OCTAL_READ flag for Macronix mx66uw2g345gx0 2Gb(256MB) NOR Flash memory. Initial testing was conducted on the Versal NET board using SDR mode, which included basic erase, write, and read-back operations. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Link: https://lore.kernel.org/r/20240508052749.214286-1-prasad.kummari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-06-17mtd: nand: pxa3xx: Incorrect bitflip return on page readRavi Minnikanti1-0/+5
Once a page is read with higher bitflips all subsequent reads are returning the same bitflip value even though they have none. max_bitflip variable is not being reset to 0 across page reads. This is causing problems like incorrectly marking erase blocks bad by UBI and causing read failures. Verified the change with both MTD reads and UBI. This change is inline with other NFC drivers. Sample error log where a block is marked bad incorrectly: ubi0: fixable bit-flip detected at PEB 125 ubi0: run torture test for PEB 125 ubi0: fixable bit-flip detected at PEB 125 ubi0 error: torture_peb: read problems on freshly erased PEB 125, must be bad ubi0 error: erase_worker: failed to erase PEB 125, error -5 ubi0: mark PEB 125 as bad Link: https://lore.kernel.org/all/ea0422cd-a8e6-3c36-f551-a0142893301b@marvell.com Signed-off-by: rminnikanti <rminnikanti@marvell.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: rminnikanti <rminnikanti@marvell.com> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-06-17ubi: Depend on MTDJohn Watts1-0/+1
UBI required MTD to build correctly, add it as a Kconfig dependency. Link: https://lore.kernel.org/all/20240411-mtd-v1-1-fe300f6ab657@jookia.org Signed-off-by: John Watts <contact@jookia.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutins.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-06-17mtd: rawnand: macronix: OTP access for MX30LFxG18ACArseniy Krasnov1-0/+170
Support for OTP area access on MX30LFxG18AC chip series. Link: https://lore.kernel.org/all/20231130112405.92196-1-avkrasnov@salutedevices.com Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-06-12mtd: spi-nor-core: Do not start or end writes at odd address in DTR modePratyush Yadav1-4/+55
On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jonathan Humphreys <j-humphreys@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini81-81/+25
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini81-25/+81
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07mtd: Remove <common.h> and add needed includesTom Rini81-81/+25
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-22Merge patch series "Kconfig: some cleanups"Tom Rini2-2/+2
Michal Simek <michal.simek@amd.com> says: I looked as cleaning up some dependencies and I found that qconfig is reporting some issues. This series is fixing some of them. But there are still some other pending. That's why please go and fix them if they are related to your board. UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in a loop you will find some other issue with copyright chars or some issues in files taken from the Linux kernel like DTs. They should be likely fixed in the kernel first. Based on discussion I am ignoring names too.
2024-04-22common: Convert *.c/h from UTF-8 to ASCII enconfingMichal Simek1-1/+1
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
2024-04-22Kconfig: Make all Kconfig encoding asciiMichal Simek1-1/+1
Some of Kconfigs are using utf-8 encoding because of used chars. Convert all of them to ascii enconging. Based on discussion ASCII should be used in general with the exception of names. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2024-04-19mtd: rawnand: stm32_fmc2: add MP25 supportChristophe Kerello1-7/+40
FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are available when on MP25 SoC, the 4 chip select are available. Let's use a platform data structure for parameters that will differ. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-04-14Merge tag 'u-boot-nand-20240414' of ↵Tom Rini8-60/+1582
https://source.denx.de/u-boot/custodians/u-boot-nand-flash The first patch is by Weizhao Ouyang and avoids sf probe crashes. The second patch is by Arseniy Krasnov and adds basic support for Amlogic Meson NAND controller on AXG. The following four patches are by Alexander Dahl and apply some fixes to drivers/mtd/nand/raw/ and port some changes applied in Linux. The following patch is by Bruce Suen and adds support for XTX SPINAND. Finally, the last patch is again by Arseniy Krasnov and adds access to OTP region, supporting info, dump, write and lock operations.
2024-04-14mtd: spinand: Add support for XTX SPINANDBruce Suen3-1/+268
Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and XT26G12D. Link: https://lore.kernel.org/all/20240312014314.15454-1-bruce_suen@163.com Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: atmel: Fix comment in timings preparationAlexander Dahl1-1/+1
Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND driver") when driver was initially ported from Linux. The context around this and especially the code itself suggests 'read' is meant instead of write. The fix is the same as accepted in Linux already with mainline Linux kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in timings preparation"). Link: https://lore.kernel.org/all/20240320090214.40465-6-ada@thorsis.com Link: https://lore.kernel.org/linux-mtd/20240307172835.3453880-1-miquel.raynal@bootlin.com/T/#t Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Fix (most) Kconfig indentationAlexander Dahl1-53/+53
One tab in general. One tab plus two spaces for help text. Link: https://lore.kernel.org/all/20240320090214.40465-4-ada@thorsis.com Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Port another option flag from LinuxAlexander Dahl1-2/+0
Introduced in upstream Linux with commit 7a08dbaedd365 for release v5.0. When the new atmel nand driver was backported to U-Boot with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND driver") that definition was added to the driver instead of the header file. Move it over to the other definitions with the same help text it has in Linux. Code actually using this has not been ported over to raw nand base yet. Link: https://lore.kernel.org/all/20240320090214.40465-3-ada@thorsis.com Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: nand: raw: Use macro nand_to_mtd() where appropriateAlexander Dahl1-3/+3
In every other place in this file the macro is used, make it consistent. Link: https://lore.kernel.org/all/20240320090214.40465-2-ada@thorsis.com Fixes: 9d1806fadc24 ("mtd: nand: Get rid of mtd variable in function calls") Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-04-14mtd: rawnand: Meson NAND controller supportArseniy Krasnov3-0/+1258
Basic support for Amlogic Meson NAND controller on AXG. This version works at only first EDO mode. Based on Linux version 6.7.0-rc4. Link: https://lore.kernel.org/all/20240210223927.570043-1-avkrasnov@salutedevices.com Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-03-12mtd: nand: arasan: Fix the crash caused by use after freeVenkatesh Yadav Abbarapu1-13/+14
The below exception observed on QEMU, as it doesn't support NAND controller. "Synchronous Abort" handler, esr 0x96000005, far 0x17acfc878 elr: 000000000803ad40 lr : 000000000805f438 (reloc) elr: 000000007fcb4d40 lr : 000000007fcd9438 x0 : 000000007bbfc880 x1 : 00000000ff100000 x2 : 000000007fcf059c x3 : 000000007bbfc870 x4 : 000000007fd9a388 x5 : 000000017acfc870 x6 : 0000000000000000 x7 : 000000007bbfd0e0 x8 : 0000000000003dd4 x9 : 000000007bbeec0c x10: 0000000000000001 x11: 0000000000003f8c x12: 000000007bbeecfc x13: 000000007bbeeeb0 x14: 000000007bbeeeb0 x15: 000000007bbee474 x16: 000000007fcef18c x17: 0000000000000000 x18: 000000007bbf9d70 x19: 000000007bbfc888 x20: 000000007bbfc870 x21: 000000007fd68ddb x22: 00000000ffffffed x23: 000000007bbfc878 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 000000007bbeed10 Code: 927ff8c1 924000c6 8b010065 f9400887 (f94004a2) Resetting CPU ... The crash is caused by the use after free. Updating the correct return codes rather than hardcoding. Fixes: 3dd0f8cccd6d ("mtd: nand: Remove hardcoded base address of nand") Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20240306033404.18537-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-03-12mtd: nand: arasan: Print warning for unsupported ecc modesVenkatesh Yadav Abbarapu1-0/+7
Currently only hw ecc is supported in U-Boot. If any other ecc mode is given in DT, it simply through an error. So better print what is being done. Revert this patch once soft ecc support is fixed in future. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20240306032703.17508-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-02-19mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80BFrieder Schrempf1-0/+1
The datasheet can be found here: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-01-31Merge tag 'u-boot-at91-2024.04-a' of ↵Tom Rini1-3/+0
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 features for the 2024.04 cycle: This set includes some DT alignments and solves a compile issue for custom nand defconfigs.
2024-01-29treewide: Remove clk_freeSean Anderson2-4/+1
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2024-01-29mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt IDTakahiro Kuwano1-0/+1
Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with Octal interface. It is a dual-die package parts and has same features with existing S28 series. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable()Takahiro Kuwano1-27/+27
Enabling Octal DTR mode in multi-die package parts requires reister setup for each die. That can be done by simple for-loop. write_enable() takes effect to all die at once so we can call it before the loop. Besides we can replace spi_mem_exec_op() calls with spansion_read/write_any_reg(). And finally, we must mask CFR2V[7:4] when changing dummy cycles, as CFR2V[7] indicates current addressing mode and that should be 1 (4-byte address mode) for multi-die package parts. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 ↵Takahiro Kuwano1-46/+6
and S28 s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size. s25_post_bfpt_fixup() is doing same thing including multi-die support. We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup() into one named s25_s28_post_bfpt_fixup(). In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing but it works actually (confirmed). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28Takahiro Kuwano1-37/+4
s28hx_t_setup() only checks sector layout setting. To support multi-die package parts like S28HS02GT, it needs to check device size and assign ready() hook for multi-die package parts. These are covered in s25_setup() so we can consolidate s28hx_t_setup() and s25_setup() into one named s25_s28_setup(). spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be removed since there is no op that makes device busy state before setup. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR modeTakahiro Kuwano1-3/+3
s25_mdp_ready() handles status polling for multi-die package parts that requires to read and check status register for each die. To support S28HS02GT(dual-die package with Octal DTR support), rename function and use nor->rdsr_dummy in octal DTR mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28Takahiro Kuwano1-1/+1
Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode. Instead, it supports CLPEF(0x82) which has the same functionality as CLSR. spansion_sr_ready() is for multi-die package parts including S28HS02GT, so we need to use CLPEF instead of CLSR. This change does not affect to S25x02GT which uses spansion_sr_ready() as S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR modeTakahiro Kuwano1-5/+29
In Infineon multi-die package parts, we need to use Read Any Register op to read status register in 2nd or further die. Infineon S28HS02GT is dual-die package and supports Octal DTR interface. To support this, spansion_read_any_reg() needs to be reworked. Implementation is similar to existing read_sr() that already supports Octal DTR mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28Takahiro Kuwano1-10/+3
s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector layout (32 x 4KB sectors overlaid at bottom address) and doing same thing. Consolidate them into single helper named s25_s28_erase_non_uniform(). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28Takahiro Kuwano1-12/+14
Some macro definitions used in Infineon(Cypress) S25 and S28 series are redundant and some have inconsistent prefix. This patch removes redundant ones and renames some to have same prefix as others. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi: spi-nor-ids: Add more XM25Q series chipsSsunk1-0/+4
- XM25QH128C - XM25QH256C - XM25QU256C - XM25QH512C - XM25QU512C Signed-off-by: Kankan Sun <ssunkkan@gmail.com> [jagan: update the commit message] Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-29mtd: spi-nor-ids: Add is25lx512 chipTejas Bhumkar1-0/+2
Added support for the ISSI OSPI flash part IS25LX512M. Initial testing was performed on the Tenzing-se1 board using SDR mode, covering basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-01-22mtd: Make CONFIG_MTD be the gate symbol for the menuTom Rini1-2/+4
The help for CONFIG_MTD explains that it needs to be enabled for various things like NAND, etc to be available. It however then doesn't enforce this dependency and so if you have none of these systems present you still need to disable a number of options. Fix this by making places that select/imply one type of flash, but did not do the same, also do this for "MTD". Make boards which hadn't been enabling MTD already but need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it wasn't previously enabled but was now being implied. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-22mtd: nand: raw: atmel: Remove duplicate definitionsAlexander Dahl1-3/+0
These removed definitions were specific to some sam9 SoCs, but not generic over all at91 SoCs. The correct SoC specific definitions for ATMEL_BASE_PMECC are spread over different header files in arch/arm/mach-at91/include/mach directory. Fixes a build error on a custon board based on SAMA5D2: Building current source for 73 boards (16 threads, 1 job per thread) arm: + vera2 +drivers/mtd/nand/raw/atmel/pmecc.c:819: warning: "ATMEL_BASE_PMECC" redefined + 819 | #define ATMEL_BASE_PMECC 0xffffe000 + | +In file included from include/configs/vera2.h:11, + from include/config.h:3, + from include/linux/mtd/rawnand.h:16, + from drivers/mtd/nand/raw/atmel/pmecc.c:44: +include/asm/arch/sama5d2.h:171: note: this is the location of the previous definition + 171 | #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +drivers/mtd/nand/raw/atmel/pmecc.c:820: warning: "ATMEL_BASE_PMERRLOC" redefined + 820 | #define ATMEL_BASE_PMERRLOC 0xffffe600 +include/asm/arch/sama5d2.h:172: note: this is the location of the previous definition + 172 | #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) Fixes: a490e1b7c017 ("nand: atmel: Add pmecc driver") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-01-15mtd: rawnand: omap_gpmc: fix OF based partition parsing for NANDRoger Quadros1-0/+2
Set NAND chip ofnode and device so OF based partition parsing can work. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499178.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: rawnand: omap_gpmc: Use DT provided IO addressRoger Quadros1-5/+14
For DM case we can get the NAND chip's IO address from DT so we don't need to rely on CFG_SYS_NAND_BASE. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499177.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: rawnand: omap_elm: Fix elm_init definitionRoger Quadros2-8/+2
The macro ELM_BASE is defined in mach/hardware.h and is not visible at the omap_elm.h header file. Avoid using it in omap_elm.h. Reported-by: Hong Guan <hguan@ti.com> Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support") Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/all/20231211114600.4414-3-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: nand: omap_gpmc: Fix NAND in SPL for AM335xRoger Quadros1-66/+29
AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader. This driver expects 1 sector at a time ECC and doesn't work well with multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Additionally, the omap_elm driver does not support multi sector ECC and will need more work and tests to get multi sector working correctly on all platforms. Switch back to 1 sector at a time read/ECC. Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Enrico Leto <enrico.leto@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Link: https://lore.kernel.org/all/20231211114600.4414-2-rogerq@kernel.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2024-01-15mtd: nand: check nand_mtd_to_devnum() argumentDario Binacchi1-1/+4
If the "mtd" parameter is NULL, the search will definitely yield a negative result. In that case, it's better to exit immediately. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102113829.58852-1-dario.binacchi@amarulasolutions.com
2024-01-15mtd: nand: complete nand_register() arguments checkDario Binacchi1-1/+1
The patch checks that the "mtd" parameter is accessible before proceeding. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102112743.57420-1-dario.binacchi@amarulasolutions.com
2023-12-18Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi ↵Tom Rini6-3/+200
into next - spi_nor_read_sfdp_dma_unsafe (Vaishnav) - w25q01/02 (Jim)
2023-12-18Merge tag 'v2024.01-rc5' into nextTom Rini2-0/+10
Prepare v2024.01-rc5
2023-12-14mtd: spi-nor-ids: add support for xtx XT55Q02GBruce Suen1-0/+2
Add support for XTX XT55Q02G(1.8V,2Gbit). Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14mtd: spinand: add support for ESMT F50x1G41LBIgor Prusov3-1/+140
Adaptation of Linux commit d74c36480a67 This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-14mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parseVaishnav Achath1-2/+32
During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-12-09mtd: spi-nor: add flash model w25q01/02 supportJim Liu1-0/+10
add flash w25q01jv, w25q01jvfim and w25q02jv support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.1 at 2024-07-08 08:18:36 +0000