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| author | Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | 2023-12-22 14:46:00 +0900 |
|---|---|---|
| committer | Jagan Teki <jagan@edgeble.ai> | 2024-01-29 19:34:17 +0530 |
| commit | 9768d7c7ecad722bdfdad72fa10a0e8a788c7a31 (patch) | |
| tree | cbbe96d4313db54968b146455a558631d7f56aea /drivers/mtd | |
| parent | a3a5cc7613ebbbd647ddd0555e0c9a23c340318e (diff) | |
| download | u-boot-9768d7c7ecad722bdfdad72fa10a0e8a788c7a31.zip u-boot-9768d7c7ecad722bdfdad72fa10a0e8a788c7a31.tar.gz u-boot-9768d7c7ecad722bdfdad72fa10a0e8a788c7a31.tar.bz2 | |
mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode
In Infineon multi-die package parts, we need to use Read Any Register op
to read status register in 2nd or further die. Infineon S28HS02GT is
dual-die package and supports Octal DTR interface. To support this,
spansion_read_any_reg() needs to be reworked. Implementation is similar
to existing read_sr() that already supports Octal DTR mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index eed3459..f24b969 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -331,12 +331,36 @@ static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, u8 *val) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), - SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 1), - SPI_MEM_OP_DUMMY(dummy / 8, 1), - SPI_MEM_OP_DATA_IN(1, NULL, 1)); + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), + SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 0), + SPI_MEM_OP_DUMMY(dummy, 0), + SPI_MEM_OP_DATA_IN(1, NULL, 0)); + u8 buf[2]; + int ret; + + spi_nor_setup_op(nor, &op, nor->reg_proto); + + /* + * In Octal DTR mode, the number of address bytes is always 4 regardless + * of addressing mode setting. + */ + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) + op.addr.nbytes = 4; + + /* + * We don't want to read only one byte in DTR mode. So, read 2 and then + * discard the second byte. + */ + if (spi_nor_protocol_is_dtr(nor->reg_proto)) + op.data.nbytes = 2; - return spi_nor_read_write_reg(nor, &op, val); + ret = spi_nor_read_write_reg(nor, &op, buf); + if (ret) + return ret; + + *val = buf[0]; + + return 0; } static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val) |