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4 dayshw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' includePhilippe Mathieu-Daudé1-1/+0
"qemu/typedefs.h" is already included by "qemu/osdep.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250708085859.7885-2-philmd@linaro.org>
6 daysMerge tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi3-2/+32
staging target-arm queue: * New board type max78000fthr * Enable use of CXL on Arm 'virt' board * Some more tidyup of ID register handling * Refactor AT insns and PMU regs into separate source files * Don't enforce NSE,NS check for EL3->EL3 returns * hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ * Allow nested-virtualization with KVM on the 'virt' board * system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict * hw/arm/virt-acpi-build: Don't create ITS id mappings by default * target/arm: Remove unused helper_sme2_luti4_4b # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhxEcoZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3j5yEACWYnNeqo8Yph6/EJExE6eV # r0tC6FBb5ShPgA6kDxhpOc1lI6uXGh8+D7bL9BePEdz/brCf1QDfs2Z4q/hb5ysX # D0H6VI5Gr1j6MjkFRBo3+vvYz4Yh++XLn5Q9lZv8zaSEdraq/ay2kxnuhRCK+4Ar # +QoGtKrGMJ7UCpfiRlvNnd1UjgORZf10EE/bRImX13sxeDomP3CZhFzAyJyShOP9 # JA7bAd4rYJ4oj8R33y8Yaxjwm4FOndj740B0zwpO8mpjzFiE5zbqsaO+mEgYSflc # OQisCu/KRFpyIR+UqP+4gNaJLfKQW5Y4r61zEaiJWV/c4RdKNnbK1f7MX11fNhOk # k1paF3GIXp6f794Hb14vtsYnKHF2eeNSmRkAomXxLgUSYzLezL+yj7cdYmRJhgYU # thc1PSiEmHYhjRmOaMC9+dkMtvIexWyDNYNFTygoOE5/kTMSazeTFQpFmw+ZuTee # 9pjKsYRZJgTa64IkJy1L34jc2gds48Q20KpQsqZ22KQcjwt4PW4eQXkvMylawSut # mArHVH6AAxIK+defeEmnQCJ0OccyGCENjRDuWyWMMGoP/ggZpO47rGWmCUOK8xz8 # IfGdPeF/9xsKSKWvjpiHyyKa48wuO2bVC+5bISS6IPA2uGneS2DpmjkHU+gHBqpk # GNlvEnXZfavZOHejE7/L/Q== # =hJ4/ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Jul 2025 09:29:46 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250711' of https://gitlab.com/pm215/qemu: (36 commits) tests/functional: Add a test for the MAX78000 arm machine docs/system: arm: Add max78000 board description target/arm: Remove helper_sme2_luti4_4b hw/arm/virt-acpi-build: Don't create ITS id mappings by default system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict hw/arm/virt: Allow virt extensions with KVM hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported target/arm/kvm: Add helper to detect EL2 when using KVM hw/arm: Allow setting KVM vGIC maintenance IRQ hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ target/arm: Don't enforce NSE,NS check for EL3->EL3 returns target/arm: Split out performance monitor regs to cpregs-pmu.c target/arm: Split out AT insns to tcg/cpregs-at.c target/arm: Drop stub for define_tlb_insn_regs arm/kvm: shorten one overly long line arm/cpu: store clidr into the idregs array arm/cpu: fix trailing ',' for SET_IDREG arm/cpu: store id_aa64afr{0,1} into the idregs array arm/cpu: store id_afr0 into the idregs array ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 dayshw/intc/loongarch_extioi: Move unrealize function to common codeBibo Mao2-9/+9
Memory about LoongArchExtIOICommonState::cpu is allocated in common code, it had better be freed in common code also. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
9 dayshw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virtEric Auger1-0/+8
We may be miss some NV related GIC register save/restore. Until we complete the study, let's add a migration blocker when the maintenance IRQ is set. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250707164129.1167837-5-eric.auger@redhat.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9 dayshw/arm: Allow setting KVM vGIC maintenance IRQHaibo Xu2-0/+22
Allow virt arm machine to set the interrupt ID for the KVM GIC maintenance interrupt. This setting must be done before the KVM_DEV_ARM_VGIC_CTRL_INIT hence the choice to perform the setting in the GICv3 realize instead of proceeding the same way as kvm_arm_pmu_set_irq(). Signed-off-by: Haibo Xu <haibo.xu@linaro.org> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250707164129.1167837-2-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9 daysarm/cpu: store clidr into the idregs arrayCornelia Huck1-1/+1
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250704141927.38963-5-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9 daysarm/cpu: store id_afr0 into the idregs arrayCornelia Huck1-1/+1
Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250704141927.38963-2-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04migration: Fix migration failure when aia is configured as aplic-imsicliu.xuemei1@zte.com.cn2-4/+18
Address an error in migration when aia is configured as 'aplic-imsic' in riscv kvm vm by adding riscv_aplic_state_needed() and riscv_imsic_state_needed() to determine whether the corresponding sates are needed. Previously, the fields in the vmsds of 'riscv_aplic' and 'riscv_imsic' can only be initialized under certain special conditions in commit 95a97b3fd2. However, the corresponding ses of these vmsds are inserted into the savevm_state.handlers unconditionally. This led to migration failure characterized by uninitialized fields when save vm state: qemu-system-riscv64: ../migration/vmstate.c:433: vmstate_save_state_v: Assertion 'first_elem || !n_elems || !size' failed. Fixes: 95a97b3fd2 ("target/riscv: update APLIC and IMSIC to support KVM AIA") Signed-off-by: Xuemei Liu <liu.xuemei1@zte.com.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250616150034827wuHs_ffe3Qm8cqFXT7HeW@zte.com.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-04hw/intc: riscv_aclint: Fix mtime write for sstc extensionJim Shu1-0/+5
When changing the mtime value, the period of [s|vs]timecmp timers should also be updated, similar to the period of mtimecmp timer. The period of the stimecmp timer is the time until the next S-mode timer IRQ. The value is calculated as "stimecmp - time". [1] It is equal to "stimecmp - mtime" since the time CSR is a read-only shadow of the memory-mapped mtime register. Thus, changing mtime value will update the period of stimecmp timer. Similarly, the period of vstimecmp timer is calculated as "vstimecmp - (mtime + htimedelta)" [2], so changing mtime value will update the period of vstimecmp timer. [1] RISC-V Priv spec ch 9.1.1. Supervisor Timer (stimecmp) Register A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers whenever time contains a value greater than or equal to stimecmp. [2] RISC-V Priv spec ch19.2.1. Virtual Supervisor Timer (vstimecmp) Register A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the hip register, whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp Signed-off-by: Jim Shu <jim.shu@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250519143518.11086-3-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-01arm/cpu: Store id_mmfr0-5 into the idregs arrayEric Auger1-4/+4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-12-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_dfr0/1 into the idregs arrayEric Auger1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-11-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_pfr0/1/2 into the idregs arrayEric Auger1-2/+3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-10-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_isar0-7 into the idregs arrayEric Auger1-6/+6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-9-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-19hw/loongarch/virt: Add reset support for kernel irqchipBibo Mao6-0/+24
When system reboot, interrupt controller is restored to initial state. However if interrupt controller extioi/ipi/pch_pic is emulated in kernel, it should notify kvm to do so. Here suspend and restore API is used for reset, set initial state in qemu user space and restore API is used to notify kvm to reload register state. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-11-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_pch: Inject irq line interrupt to kernelBibo Mao1-0/+5
If kvm_irqchip_in_kernel() return true, irq line interrupt can be injected with API kvm_set_irq() to KVM. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-10-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_pch: Add kernel irqchip save and restore functionBibo Mao2-0/+69
Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set PCH PCI irqchip state from KVM kernel. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_pch: Add kernel irqchip realize functionBibo Mao3-4/+50
Function kvm_pic_realize() is added if kvm_irqchip_in_kernel() return true. It is to notify KVM kernel to create and initialize PCH PCI device in kernel mode. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-8-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_pch_msi: Inject MSI interrupt to kernelBibo Mao1-0/+10
If kvm_irqchip_in_kernel() return true, MSI interrupt can be injected with API kvm_irqchip_send_msi() to KVM. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_ipi: Add kernel irqchip save and restore functionBibo Mao2-0/+74
Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set IPI irqchip state from KVM kernel. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-6-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongson_ipi: Add load and save interface with ipi_common classBibo Mao1-0/+28
Add pre_save and post_load interfaces with ipi_common class, here only framework ipi_common adds these interfaces. The defailed implementation is LoongArchIPI child device in later. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_ipi: Add kernel irqchip realize functionBibo Mao4-0/+39
Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true. It is to create and initialize IPI device in kernel mode. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_extioi: Add kernel irqchip save and restore functionBibo Mao2-0/+104
Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set ExtIOI irqchip state from KVM kernel. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-19hw/intc/loongarch_extioi: Add kernel irqchip realize functionBibo Mao3-12/+67
Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is set. It is to create and initialize ExtIOI device in kernel mode. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-06-16hw/intc/arm_gic: introduce a first-cpu-index propertyFrederic Konrad2-1/+2
This introduces a first-cpu-index property to the arm-gic, as some SOCs could have two separate GIC (ie: the zynqmp). Signed-off-by: Clément Chigot <chigot@adacore.com> Message-id: 20250526085523.809003-3-chigot@adacore.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: slightly expanded comment documenting GIC property] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-10hw/intc/loongarch_pch: Convert to little endian with ID registerBibo Mao1-1/+1
With PCH ID register, it is defined as union type as follows: union LoongArchPIC_ID { struct { uint8_t _reserved_0[3]; uint8_t id; uint8_t version; uint8_t _reserved_1; uint8_t irq_num; uint8_t _reserved_2; } QEMU_PACKED desc; uint64_t data; } And with pch driver in virt machine irq_number is parsed with little endian method: vec_count = ((readq(priv->base) >> 48) & 0xff) + 1 So the value of ID register should be converted to little endian. With this patch, linux kernel passes to run on S390 big endian host machine with TCG method. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250604065502.1114098-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-25hw/intc/aspeed Fix coding styleJamin Lin1-2/+4
Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250522023305.2486536-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-25hw/intc/aspeed: Set impl.min_access_size to 4Jamin Lin1-0/+6
This patch explicitly sets ".impl.min_access_size = 4" to match the declared ".valid.min_access_size = 4", enforcing stricter access size checking and preventing inconsistent partial accesses to the interrupt controller registers. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250522023305.2486536-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-14hw/arm: Replace TABs for spaces in OMAP board and device codeSantiago Monserrat Campanello1-77/+77
In hw/arm and include/hw/arm, some source files for the OMAP SoC and the sx1 boards that are our only remaining OMAP boards still have hard-coded tabs (almost entirely used for the indent on inline comments, not for actual code indent). Replace the tabs with spaces using vim :retab. I used 4 spaces except in some defines and comments where I tried to put everything aligned in the same column for better readability. This commit is a purely whitespace-only change. Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> Message-id: 20250505131130.82206-1-santimonserr@gmail.com Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373 [PMM: expanded commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14hw/intc/loongarch_pch: Merge three memory region into oneBibo Mao1-65/+1
Since memory region iomem supports memory access size with 1/2/4/8, it can be used for memory region iomem8 and iomem32_high. Now remove memory region iomem8 and iomem32_high, merge them into iomem together. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Set flexible memory access size with iomem regionBibo Mao1-3/+10
The original iomem region only supports 4 bytes access size, set it ok with 1/2/4/8 bytes. Also unaligned memory access is not supported. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Rename memory region iomem32_low with iomemBibo Mao1-19/+7
Rename memory region iomem32_low with iomem, also change ops name as follows: loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops loongarch_pch_pic_low_readw --> loongarch_pch_pic_read loongarch_pch_pic_low_writew --> loongarch_pch_pic_write Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use unified trace event for memory region opsBibo Mao2-24/+8
Add trace event trace_loongarch_pch_pic_read(), replaces the following three events: trace_loongarch_pch_pic_low_readw() trace_loongarch_pch_pic_high_readw() trace_loongarch_pch_pic_readb() The similiar with write trace event. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic write callback for iomem8 regionBibo Mao1-21/+10
Add iomem8 region register write operation emulation in generic write function loongarch_pch_pic_write(), and use this function for iomem8 region. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023754.1877445-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic write callback for iomem32_high regionBibo Mao1-23/+5
Add iomem32_high region register write operation emulation in generic write function loongarch_pch_pic_write(), and use this function for iomem32_high region. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-12-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic write callback for iomem32_low regionBibo Mao1-67/+73
For memory region iomem32_low, generic write callback is used. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-11-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic read callback for iomem8 regionBibo Mao1-20/+8
Add iomem8 region register read operation emulation in generic read function loongarch_pch_pic_read(), and use this function for iomem8 region. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-10-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic read callback for iomem32_high regionBibo Mao1-19/+8
Add register read operation emulation in generic read function loongarch_pch_pic_read(), and use this function for iomem32_high region. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use generic read callback for iomem32_low regionBibo Mao1-20/+47
For memory region iomem32_low, generic read callback is used. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-8-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Discard write operation with ISR registerBibo Mao1-6/+0
With the latest 7A1000 user manual, interrupt status register ISR is read only. Here discard write operation with ISR register. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-7-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Use relative address in MemoryRegionOpsBibo Mao1-18/+16
Parameter address for read and write callback in MemoryRegionOps is relative offset with base address of this MemoryRegionOps. It can be directly used as offset and offset calculation can be removed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-6-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Set version information at initial stageBibo Mao2-7/+15
Register PCH_PIC_INT_ID constains version and supported irq number information, and it is read only register. The detailed value can be set at initial stage, rather than read callback. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Remove some duplicate macroBibo Mao1-10/+10
The meaning of macro definition STATUS_LO_START is simliar with PCH_PIC_INT_STATUS, only that offset is different, the same for macro POL_LO_START. Now remove these duplicated macro definitions. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with PCH_PIC_xxxBibo Mao1-10/+10
Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to understand. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-14hw/intc/loongarch_pch: Modify name of some registersBibo Mao1-24/+26
For some registers with width 8 bytes, its name is something like PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual, register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2025-05-06Merge tag 'pull-loongarch-20250506' of https://github.com/bibo-mao/qemu into ↵Stefan Hajnoczi5-22/+111
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaBljTgAKCRAfewwSUazn # 0cSzAPoCbqppm5lUPgFAacD4m1sUI6jLk5pJGMsQTQHkMZ34yQD7BswZhMWPL44Z # LmrZgO7NfqAv96AF1mpRawV9ZXSOGAQ= # =3itp # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 May 2025 21:18:06 EDT # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250506' of https://github.com/bibo-mao/qemu: hw/loongarch/virt: Allow user to customize OEM ID and OEM table ID hw/loongarch/virt: Replace RSDT with XSDT table hw/loongarch/virt: Get physical entry address with elf file hw/intc/loongarch_pch: Replace legacy reset callback with new api hw/intc/loongarch_pch: Add reset support hw/intc/loongarch_extioi: Replace legacy reset callback with new api hw/intc/loongarch_extioi: Add reset support hw/intc/loongarch_ipi: Add reset support Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-06hw/intc/loongarch_pch: Replace legacy reset callback with new apiBibo Mao1-18/+8
Replace legacy reset callback register device_class_set_legacy_reset() with new function resettable_class_set_parent_phases(). With new API, it will call reset callback of parent object. The internal state has been cleared in parent object LOONGARCH_PIC_COMMON, here parent_phases.hold() is directly called. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_pch: Add reset supportBibo Mao1-0/+25
Add reset support with LoongArch pci irqchip, and register reset callback support with new API resettable_class_set_parent_phases(). Clear internal HW registers and SW state when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_extioi: Replace legacy reset callback with new apiBibo Mao1-4/+8
Replace legacy reset callback register device_class_set_legacy_reset() with new function resettable_class_set_parent_phases(). With new API, it will call reset callback of parent object and then itself. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_extioi: Add reset supportBibo Mao1-0/+41
Add reset support with extioi irqchip, and register reset callback support with new API resettable_class_set_parent_phases(). Clear internal HW registers and SW state when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-05-06hw/intc/loongarch_ipi: Add reset supportBibo Mao1-0/+29
Add reset support with ipi object, register reset callback and clear internal registers when virt machine resets. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
generated by cgit v1.1 at 2025-07-19 00:56:58 +0000