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5 daysMerge tag 'pull-target-arm-20250801' of https://gitlab.com/pm215/qemu into st...Stefan Hajnoczi1-4/+2
8 dayshw/intc/arm_gicv3_kvm: Write all 1's to clear enable/activeZenghui Yu1-1/+1
8 dayshw/intc/arm_gicv3_kvm: Remove writes to ICPENDR registersZenghui Yu1-3/+1
9 dayshw/intc/loongarch_ipi: Fix start fail with smp cpu < smp maxcpus on KVMSong Gao1-11/+16
10 daysintc/riscv_aplic: Fix target register read when source is inactiveYang Jialong1-1/+5
2025-07-21ppc/xive2: Enable lower level contexts on VP pushNicholas Piggin1-8/+28
2025-07-21ppc/xive: Split need_resend into restore_nvpNicholas Piggin2-24/+28
2025-07-21ppc/xive2: Implement PHYS ring VP push TIMA opNicholas Piggin2-0/+13
2025-07-21ppc/xive2: Implement POOL LGS push TIMA opNicholas Piggin1-0/+8
2025-07-21ppc/xive2: Implement set_os_pending TIMA opNicholas Piggin2-0/+30
2025-07-21ppc/xive2: redistribute group interrupts on context pushNicholas Piggin1-1/+7
2025-07-21ppc/xive2: Implement pool context push TIMA opNicholas Piggin2-17/+37
2025-07-21ppc/xive: Check TIMA operations validityNicholas Piggin1-81/+115
2025-07-21ppc/xive: Redistribute phys after pulling of pool contextNicholas Piggin2-2/+17
2025-07-21ppc/xive2: Prevent pulling of pool context losing phys interruptNicholas Piggin1-8/+10
2025-07-21ppc/xive2: implement NVP context save restore for POOL ringNicholas Piggin1-16/+35
2025-07-21ppc/xive: Assert group interrupts were redistributedNicholas Piggin2-0/+3
2025-07-21ppc/xive2: Avoid needless interrupt re-check on CPPR setNicholas Piggin1-1/+3
2025-07-21ppc/xive2: Consolidate presentation processing in context pushNicholas Piggin1-32/+10
2025-07-21ppc/xive2: split tctx presentation processing from set CPPRNicholas Piggin1-61/+76
2025-07-21ppc/xive: Add xive_tctx_pipr_set() helper functionNicholas Piggin2-37/+18
2025-07-21ppc/xive: tctx_accept only lower irq line if an interrupt was presentedNicholas Piggin1-2/+1
2025-07-21ppc/xive: tctx signaling registers reworkNicholas Piggin2-105/+101
2025-07-21ppc/xive: Split xive recompute from IPB functionNicholas Piggin1-3/+22
2025-07-21ppc/xive: Fix high prio group interrupt being preempted by low prio VPNicholas Piggin1-1/+17
2025-07-21ppc/xive: Add xive_tctx_pipr_present() to present new interruptNicholas Piggin2-2/+8
2025-07-21ppc/xive2: Redistribute group interrupt preempted by higher priority interruptNicholas Piggin1-2/+12
2025-07-21ppc/xive: Change presenter .match_nvt to match not presentNicholas Piggin5-74/+58
2025-07-21ppc/xive2: redistribute irqs for pool and phys ctx pullGlenn Miles2-33/+73
2025-07-21ppc/xive2: Redistribute group interrupt precluded by CPPR updateGlenn Miles1-22/+60
2025-07-21ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA opGlenn Miles2-3/+55
2025-07-21ppc/xive2: Improve pool regs variable nameGlenn Miles1-6/+5
2025-07-21ppc/xive: Add more interrupt notification tracingGlenn Miles3-5/+17
2025-07-21ppc/xive2: Support redistribution of group interruptsGlenn Miles1-4/+80
2025-07-21ppc/xive2: add interrupt priority configuration flagsGlenn Miles2-4/+13
2025-07-21pnv/xive2: Permit valid writes to VC/PC Flush Control registersMichael Kowal1-4/+32
2025-07-21pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULLNicholas Piggin1-1/+0
2025-07-21pnv/xive2: Print value in invalid register write loggingMichael Kowal1-8/+16
2025-07-21pnv/xive2: Support ESB EscalationGlenn Miles1-12/+50
2025-07-21ppc/xive: Fix pulling pool and phys contextsNicholas Piggin1-8/+58
2025-07-21ppc/xive: Move NSR decoding into helper functionsNicholas Piggin1-9/+42
2025-07-21ppc/xive: Explicitly zero NSR after acceptingNicholas Piggin1-4/+2
2025-07-21ppc/xive: tctx_notify should clear the precluded interruptNicholas Piggin1-0/+3
2025-07-21ppc/xive2: Set CPPR delivery should account for group priorityNicholas Piggin1-10/+22
2025-07-21ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPRNicholas Piggin1-1/+3
2025-07-21ppc/xive2: Fix treatment of PIPR in CPPR updateGlenn Miles1-1/+3
2025-07-21ppc/xive2: Fix irq preempted by lower priority group irqGlenn Miles1-1/+1
2025-07-21ppc/xive2: Use fair irq target search algorithmGlenn Miles1-2/+16
2025-07-21ppc/xive2: Reset Generation Flipped bit on END Cache WatchMichael Kowal2-3/+4
2025-07-21ppc/xive: Fix PHYS NSR ring matchingNicholas Piggin1-1/+2
generated by cgit v1.1 at 2025-08-09 04:13:58 +0000