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2 daysMerge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell3-4/+43
staging pull-loongarch-20241016 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZw91kQAKCRBAov/yOSY+ # 3+RyA/9vpqCesEBch5mzrazO4MT2IxeN2bstF8mY+EyfEwK7Ocg+esRBsigWw56k # y6RDyCzHg200GL9TC8bJ/nMiMJjXrahhHRPVs8AADazMzX/Ys7E7ntvUUnqqANh6 # ZX8fzNJMKW6qeUVrCIwCC7E+KjfNu32dcxbXCF4mZsehIumpUQ== # =uk+a # -----END PGP SIGNATURE----- # gpg: Signature made Wed 16 Oct 2024 09:13:05 BST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu: hw/loongarch/fw_cfg: Build in common_ss[] hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion target/loongarch: Avoid bits shift exceeding width of bool type hw/loongarch/virt: Add FDT table support with acpi ged pm register acpi: ged: Add macro for acpi sleep control register Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysMerge tag 'single-binary-20241015' of https://github.com/philmd/qemu into ↵Peter Maydell9-43/+53
staging Remove some target-specific endianness knowledge from target/. For MIPS, propagate endianness at the board level, using QOM property. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcOihcACgkQ4+MsLN6t # wN4VaRAAor+5gUJiV0OOMQVfP8e1o9ssKcYy9m31zLeii1Iq2M/2oz6YK4OjdQDe # oJ8VRJvBPKC2Bpi14TfKsSGaP8CGNO/hdxcMi71pjHZC+bjHt5Uv0U/7T4XCBWuV # N+85juN1PTc4cci4FkGIXaPB1YWL00L56BDCzja0uhLF4+Xe2eYGVrPXeFCkN/3I # Ky7jHlB/dgzc47kTXvg5snCee2egDFf/x4igwZj6+gWJyo+jubRpwoOqKbK2M0Nd # VvNpBVFNGZMP3Fn9lh45uDOuRWGu6zSIPBVkjoFc+wdGsFsITIMrZ3h46UffsGTJ # F1j6Zsq6hoLbaNRRjZ6OsN6u683oo1lknmWauD62LrjXcX0RlRwRFbMD0AjedR8t # 6+YHg5LlwGg6r/AOtEe28ggXZohB2vjr2V0MJm1x/XgLYhFHoN3//jxn22oOHj4p # 0z3+eDc3Se8JNRV6jPMHbbuTqZqZjRgVFbYN3aMbdoXYzhpYnrPj6f7WQL2smiAW # C2vdswrubQWKou1wcn6rbg0nnMRVTh+GxrtZ3mkgaxNzgNFxsrX8YubMsh77XUcr # mnCGj1tE3hp40xsuSk6yZXY3ZZiTyZasvO1wq4gWOI9le0Zmq+d335F9+IVJ8RlP # YhA+MY5aeomsixVRdmrPrgOfanQiHXv02lsbperU8QFfGRhf2Y8= # =Qydb # -----END PGP SIGNATURE----- # gpg: Signature made Tue 15 Oct 2024 16:28:23 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'single-binary-20241015' of https://github.com/philmd/qemu: (33 commits) hw/mips: Have mips_cpu_create_with_clock() take an endianness argument hw/mips/cps: Set the vCPU 'cpu-big-endian' property target/mips: Expose MIPSCPU::is_big_endian property target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() target/mips: Use gen_op_addr_addi() when possible target/mips: Have gen_addiupc() expand $pc during translation target/mips: Replace MO_TE by mo_endian() target/mips: Introduce mo_endian() helper target/mips: Remove unused MEMOP_IDX() macro target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() target/mips: Explode MO_TExx -> MO_TE | MO_xx target/mips: Factor mo_endian_rev() out of MXU code target/mips: Convert mips16e decr_and_load/store() macros to functions target/mips: Replace MO_TE by mo_endian_env() in get_pte() target/mips: Introduce mo_endian_env() helper target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() target/mips: Declare mips_env_is_bigendian() in 'internal.h' hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl() target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/loongarch/fw_cfg: Build in common_ss[]Philippe Mathieu-Daudé1-1/+1
Nothing in LoongArch fw_cfg.c requires target specific definitions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240927213254.17552-3-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
3 dayshw/loongarch/virt: Add FDT table support with acpi ged pm registerBibo Mao1-0/+39
ACPI ged is used for power management on LoongArch virt platform, in general it is parsed from acpi table. However if system boot directly from elf kernel, no UEFI bios is provided and acpi table cannot be used also. Here acpi ged pm register is exposed with FDT table, it is compatbile with syscon method in FDT table, only that acpi ged pm register is accessed with 8-bit mode, rather with 32-bit mode. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240918014206.2165821-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
3 daysacpi: ged: Add macro for acpi sleep control registerBibo Mao1-3/+3
Macro definition is added for acpi sleep control register, ged emulation driver can use the macro , also it can be used in FDT table if ged is exposed with FDT table. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240918014206.2165821-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
4 dayshw/mips: Have mips_cpu_create_with_clock() take an endianness argumentPhilippe Mathieu-Daudé5-5/+8
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU endianness requested by argument. Update the board call sites. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241010215015.44326-17-philmd@linaro.org>
4 dayshw/mips/cps: Set the vCPU 'cpu-big-endian' propertyPhilippe Mathieu-Daudé2-0/+6
Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241010215015.44326-16-philmd@linaro.org>
4 dayshw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ryPhilippe Mathieu-Daudé1-5/+7
Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240930073450.33195-8-philmd@linaro.org>
4 dayshw/i386: Use explicit little-endian LD/ST APIPhilippe Mathieu-Daudé2-33/+32
The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/i386/); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-9-philmd@linaro.org>
4 dayshw/arm/xilinx_zynq: Add various missing unimplemented devicesChao Liu1-0/+70
Add unimplemented-device blocks to the xilinx_zynq board corresponding to various devices documented in the TRM and in the device tree. See: ug585-Zynq-7000-TRM manual B.3 (Module Summary) Signed-off-by: Chao Liu <chao.liu@yeah.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message. Removed the clearing of the ignore_memory_transaction_failures flag] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/block: Remove eccPeter Maydell5-97/+0
The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices, which we have removed, so it is now completely unused. Note that hw/misc/eccmemctl.c does not in fact use any of the code frome ecc.c, so that KConfig dependency was incorrect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003140010.1653808-6-peter.maydell@linaro.org
4 dayshw: Remove PCMCIA subsystemPeter Maydell5-29/+0
The only PCMCIA subsystem was the PXA2xx SoC and the machines using it, which have now been removed. Although in theory we have a few machine types which have PCMCIA (e.g. kzm, the strongarm machines, sh4's sh7750), none of those machines implement their PCMCIA controller, and they're all old and no longer very interesting machine types. Rather than keeping all the PCMCIA code in-tree without any active users of it, delete it. If we need PCMCIA in future we can always resurrect it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241003140010.1653808-5-peter.maydell@linaro.org
4 dayshw/ide: Remove DSCM-1XXXX microdrive device modelPeter Maydell3-651/+0
The DSCM-1XXXX microdrive device model was used only by the XScale-based Zaurus machine types. Now they have been removed, we can delete this device too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003140010.1653808-4-peter.maydell@linaro.org
4 dayshw/gpio: Remove MAX7310 devicePeter Maydell3-222/+0
The MAX7310 GPIO controller was used only by the XScale-based Zaurus machine types. Now they have been removed we can remove this device model as well. Because this device is an I2C device, in theory it could be created by users on the command line for boards with a different I2c controller, but we don't believe users are doing this -- it would be impossible on the command line to connect up the GPIO inputs/outputs. The only example a web search produces for "device max7310" is a user trying to create this because they didn't realize that there was no way to manipulate the GPIO lines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003140010.1653808-3-peter.maydell@linaro.org
4 dayshw/adc: Remove MAX111X devicePeter Maydell3-240/+0
The MAX111X ADC device was used only by the XScale-based Zaurus machine types. Now they have all been removed, we can drop this device model too. Because this device is an SSI device, in theory it could be created by users on the command line for boards with a different SSI controller, but we don't believe users are doing this -- it would be impossible on the command line to connect up the GPIO inputs which correspond to ADC inputs, or the GPIO output which is an interrupt line. The only example a web search produces for "device max1111" or "device max1110" is our own bug report https://gitlab.com/qemu-project/qemu/-/issues/2228 where it's used as an example of a bogus command that causes an assertion in an aspeed machine type that wasn't expecting anything other than flash devices on its SMC bus. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003140010.1653808-2-peter.maydell@linaro.org
4 daysinclude: Move QemuLockCnt APIs to their own headerPeter Maydell1-0/+1
Currently the QemuLockCnt data structure and associated functions are in the include/qemu/thread.h header. Move them to their own qemu/lockcnt.h. The main reason for doing this is that it means we can autogenerate the documentation comments into the docs/devel documentation. The copyright/author in the new header is drawn from lockcnt.c, since the header changes were added in the same commit as lockcnt.c; since neither thread.h nor lockcnt.c state an explicit license, the standard default of GPL-2-or-later applies. We include the new header (and the .c file, which was accidentally omitted previously) in the "RCU" part of MAINTAINERS, since that is where the lockcnt.rst documentation is categorized. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20240816132212.3602106-7-peter.maydell@linaro.org
4 dayshw/char/pl011: Use correct masks for IBRD and FBRDPeter Maydell1-2/+2
In commit b88cfee90268cad we defined masks for the IBRD and FBRD integer and fractional baud rate divider registers, to prevent the guest from writing invalid values which could cause division-by-zero. Unfortunately we got the mask values the wrong way around: the FBRD register is six bits and the IBRD register is 16 bits, not vice-versa. You would only run into this bug if you programmed the UART to a baud rate of less than 9600, because for 9600 baud and above the IBRD value will fit into 6 bits, as per the table in https://developer.arm.com/documentation/ddi0183/g/programmers-model/register-descriptions/fractional-baud-rate-register--uartfbrd The only visible effects would be that the value read back from the register by the guest would be truncated, and we would print an incorrect baud rate in the debug logs. Cc: qemu-stable@nongnu.org Fixes: b88cfee90268 ("hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2610 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20241007144732.2491331-1-peter.maydell@linaro.org
4 dayshw/intc/omap_intc: Remove now-unnecessary abstract base classPeter Maydell1-9/+2
The OMAP interrupt controller code used to have an omap-intc class and an omap2-intc class, which shared common code via the abstract class common-omap-intc. Now we have deleted omap2-intc, we don't need the separate abstract base class; fold int into omap-intc. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003135323.1653230-1-peter.maydell@linaro.org
4 dayshw/arm: Add SPI to Allwinner A10Strahinja Jankovic2-0/+9
The Allwinner A10 SPI controller is added to the Allwinner A10 description, so it is available when Cubieboard is emulated. Update the documentation for Cubieboard to indicate SPI availability. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20241001221349.8319-3-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/ssi: Allwinner A10 SPI emulationStrahinja Jankovic4-0/+576
This patch implements Allwinner A10 SPI controller emulation. Only master-mode functionality is implemented. Since U-Boot and Linux SPI drivers for Allwinner A10 perform only byte-wide CPU access (no DMA) to the transmit and receive registers of the peripheral, the emulated controller does not implement DMA control, and supports only byte-wide access to transmit and receive registers (half-word and word accesses will be treated as byte accesses). Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20241001221349.8319-2-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/clock: Expose 'qtest-clock-period' QOM property for QTestsInès Varhol1-0/+16
Expose the clock period via the QOM 'qtest-clock-period' property so it can be used in QTests. This property is only accessible in QTests (not via HMP). Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20241003081105.40836-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/misc: Create STM32L4x5 SYSCFG clockInès Varhol2-2/+19
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20241003081105.40836-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/intc/arm_gicv3_cpuif: Add cast to match the documentationAlexandra Diupina1-1/+1
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved. Add an explicit cast to match the documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs") Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/intc/arm_gicv3: Add cast to match the documentationAlexandra Diupina1-1/+1
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICC_AP[0/1]R<n>_EL2 are reserved. Add an explicit cast to match the documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: 28cca59c46 ("hw/intc/arm_gicv3: Add NMI handling CPU interface registers") Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/intc/arm_gicv3: Add cast to match the documentationAlexandra Diupina1-1/+1
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. When cast to uint64_t (for further bitwise OR), the 32 most significant bits will be filled with 1s. However, the documentation states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved. Add an explicit cast to match the documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: d2c0c6aab6 ("hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()") Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/arm/stm32f405: Add RCC device to stm32f405 SoCRomán Cárdenas Rodríguez2-1/+12
Add the reset and clock controller device to the stm32f405 SoC. Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com> [PMM: tweak commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCsRomán Cárdenas Rodríguez4-0/+172
Generic RCC class for STM32 devices. It can be used for most of the STM32 chips. Note that it only implements enable and reset capabilities. Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com> [PMM: tweaked commit message, added MAINTAINERS lines] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4 dayshw/arm/omap1: Remove unused omap_uwire_attach() methodPhilippe Mathieu-Daudé1-21/+8
The recently removed 'cheetah' machine was the single user of the omap_uwire_attach() method. Remove it altogether with the uWireSlave structure. Replace the send/receive callbacks by Unimplemented logging. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5 daysui: refactor using a common qemu_pixman_shareableMarc-André Lureau1-53/+19
Use a common shareable type for win32 & unix, and helper functions. This simplify the code as it avoids a lot of #ifdef'ery. Note: if it helps review, commits could be reordered to introduce the common type before introducing shareable memory for unix. Suggested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-19-marcandre.lureau@redhat.com>
5 daysvirtio-gpu: allocate shareable 2d resources on !win32Marc-André Lureau1-12/+27
Similar to what was done in commit 9462ff46 ("virtio-gpu/win32: allocate shareable 2d resources/images") for win32, allocate resource memory with memfd, so the associated display surface memory can be shared with a different process. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-18-marcandre.lureau@redhat.com>
5 daysui/pixman: generalize shared_image_destroyMarc-André Lureau1-2/+2
Learn to free memfd-allocated shared memory. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-10-marcandre.lureau@redhat.com>
5 daysui/win32: fix potential use-after-free with dbus shared memoryMarc-André Lureau1-12/+2
DisplaySurface may be free before the pixman image is freed, since the image is refcounted and used by different objects, including pending dbus messages. Furthermore, setting the destroy function in create_displaysurface_from() isn't appropriate, as it may not be used, and may be overriden as in ramfb. Set the destroy function when the shared handle is set, use the HANDLE directly for destroy data, using a single common helper qemu_pixman_win32_image_destroy(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-5-marcandre.lureau@redhat.com>
5 dayshw/audio/hda: fix memory leak on audio setupMarc-André Lureau1-13/+20
When SET_STREAM_FORMAT is called, we should clear the existing setup. Factor out common function to close a stream. Direct leak of 144 byte(s) in 3 object(s) allocated from: #0 0x7f91d38f7350 in calloc (/lib64/libasan.so.8+0xf7350) (BuildId: a4ad7eb954b390cf00f07fa10952988a41d9fc7a) #1 0x7f91d2ab7871 in g_malloc0 (/lib64/libglib-2.0.so.0+0x64871) (BuildId: 36b60dbd02e796145a982d0151ce37202ec05649) #2 0x562fa2f447ee in timer_new_full /home/elmarco/src/qemu/include/qemu/timer.h:538 #3 0x562fa2f4486f in timer_new /home/elmarco/src/qemu/include/qemu/timer.h:559 #4 0x562fa2f448a9 in timer_new_ns /home/elmarco/src/qemu/include/qemu/timer.h:577 #5 0x562fa2f47955 in hda_audio_setup ../hw/audio/hda-codec.c:490 #6 0x562fa2f4897e in hda_audio_command ../hw/audio/hda-codec.c:605 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-3-marcandre.lureau@redhat.com>
5 dayshw/audio/hda: free timer on exitMarc-André Lureau1-1/+1
Fixes: 280c1e1cd ("audio/hda: create millisecond timers that handle IO") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241008125028.1177932-2-marcandre.lureau@redhat.com>
8 daysMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-10/+20
* first commit for Rust support * add CI job using Fedora + Rust nightly * fix detection of ATOMIC128 on x86_64 * fix compilation with Sphinx 8.1.0 # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmcJEKUUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOSZQf+LlvZm9npHR6lZ9DEruhu/uf0c1gO # 9+dBJiKQ1OWopSQOqEgOsLL0J123Ls4V8O3tzZwIDuuRofCB2+wKswad6CHoydJx # 4p9rRXv6MLlnTqqGxemm/dPZqJ7+6L0poHoDKW+s7AgfVDshhj1RSbQfs8Ujh41F # f1sdi3DzopVWtK4CE+8/UeLy5Cxlixke9SKhYQrFHrdsANARP81gxQjczKApMc1z # v9qkrLtkM06VUyuvbPps7CHSHDpzx9mXcmkkPgLqLX9MfbCztzi44aVSaS9HYk5G # y54dSKdY7VJEuGhG916G+GMDJyow4nhT9Gk6tWtk63TQN5nExVsoZMOmdw== # =PFGL # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Oct 2024 12:48:53 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: docs: use consistent markup for footnotes docs: avoid footnotes consisting of just URLs docs: fix invalid footnote syntax gitlab-ci: add Rust-enabled CI job dockerfiles: add a Dockerfile using a nightly Rust toolchain meson: ensure -mcx16 is passed when detecting ATOMIC128 meson: define qemu_isa_flags meson: fix machine option for x86_version rust: add PL011 device model rust: add utility procedural macro crate scripts/archive-source: find directory name for subprojects rust: add crate to expose bindings and interfaces meson.build: add HAVE_GLIB_WITH_ALIGNED_ALLOC flag .gitattributes: add Rust diff and merge attributes rust: add bindgen step as a meson dependency configure, meson: detect Rust toolchain build-sys: Add rust feature option Require meson version 1.5.0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 daysrust: add PL011 device modelPaolo Bonzini1-10/+20
This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=aarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Co-authored-by: Junjie Mao <junjie.mao@intel.com> Co-authored-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Junjie Mao <junjie.mao@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Link: https://lore.kernel.org/r/6ec1d4fb8db2a1d7ba94c73e65d9770371b7857d.1727961605.git.manos.pitsidianakis@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 dayshw/s390x: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé2-85/+85
The S390X architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/s390x/); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241004163042.85922-23-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
12 dayshw/m68k: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé4-18/+18
The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/m68k/); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241004163042.85922-18-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell59-1574/+230
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-nested-aio-poll with LTO * kvm: refactoring of VM creation * target/i386: expose IBPB-BRTYPE and SBPB CPUID bits to the guest * hw/char: clean up serial * remove virtfs-proxy-helper * target/i386/kvm: Report which action failed in kvm_arch_put/get_registers * qom: improvements to object_resolve_path*() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmb++MsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPVnwf/cdvfxvDm22tEdlh8vHlV17HtVdcC # Hw334M/3PDvbTmGzPBg26lzo4nFS6SLrZ8ETCeqvuJrtKzqVk9bI8ssZW5KA4ijM # nkxguRPHO8E6U33ZSucc+Hn56+bAx4I2X80dLKXJ87OsbMffIeJ6aHGSEI1+fKVh # pK7q53+Y3lQWuRBGhDIyKNuzqU4g+irpQwXOhux63bV3ADadmsqzExP6Gmtl8OKM # DylPu1oK7EPZumlSiJa7Gy1xBqL4Rc4wGPNYx2RVRjp+i7W2/Y1uehm3wSBw+SXC # a6b7SvLoYfWYS14/qCF4cBL3sJH/0f/4g8ZAhDDxi2i5kBr0/5oioDyE/A== # =/zo4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Oct 2024 21:04:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) qom: update object_resolve_path*() documentation qom: set *ambiguous on all paths qom: rename object_resolve_path_type() "ambiguousp" target/i386/kvm: Report which action failed in kvm_arch_put/get_registers kvm: Allow kvm_arch_get/put_registers to accept Error** accel/kvm: refactor dirty ring setup minikconf: print error entirely on stderr 9p: remove 'proxy' filesystem backend driver hw/char: Extract serial-mm hw/char/serial.h: Extract serial-isa.h hw: Remove unused inclusion of hw/char/serial.h target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest kvm: refactor core virtual machine creation into its own function kvm/i386: replace identity_base variable with a constant kvm/i386: refactor kvm_arch_init and split it into smaller functions kvm: replace fprintf with error_report()/printf() in kvm_init() kvm/i386: fix return values of is_host_cpu_intel() kvm/i386: make kvm_filter_msr() and related definitions private to kvm module hw/i386/pc: Add a description for the i8042 property tests/unit: remove block layer code from test-nested-aio-poll ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/Kconfig # hw/arm/pxa2xx.c
2024-10-04Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingPeter Maydell12-139/+1
trivial patches for 2024-10-04 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmcAEU0ACgkQgqpKJDse # lHgJlhAAmDwxXcHIeNgyOxSmopgKC5VKmux1qvi3PNmM46CGYTDG3s4MIUIRPNhi # zoLQhSdjcFNQi133WoXAWZInTwYCeEe4JbWev7bTDZxoJvZFss6P/DhmSY7tCnaf # QU+XeNl86Iy28glZjiL9EFZi7SM9+OWVF5Dqxd2NlCNA6OlnAtHoVp3bHUqkVgr1 # Lhq+0GRsxhU9bg3eO+yGXVquuOtSMa5LjEqP6kUe6ajo1E4/+GqO9hvfaj8K35Da # B5wa39/MnSN0alnNS8rJUJXxBp2hZt8VamntL86v4kMLQCVGR+KL5FmApZzxzM/r # fY8Ky4b5w8U0BDXnwCcr3A2bYlurC7FhDgBJw3YCQNwbxQbbG7PfbMATD86nfZPd # HTjDjn874reGXgdXt15+3q1zm8kDylMZxEJpRdmsB+uYFVDlNCimPcCPe1YSjVcW # AR5/NubrigpuX8qM5tSiLhjoeAZ0vQjoapGs5zi2dQtg4MltRgi32HPIRq3ooUUg # T2XBhDUElrwwftGQuDN6Vt5Z0EQPP6HDoFLz0VhzWvlsR5DOLjxK4oLsDmQoV34n # 9I4wSmFzwX0Vy0QJIjL6LFec/Ky8uO7QAX5PCLcsEnZy+/q2GsSdwXCPT+SPJ1AL # bEfqLw7U6CSv/eiGOpScCnCLENrw3GXrN31SqtOtgxDPj2lVEsU= # =HYZX # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Oct 2024 17:01:17 BST # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [full] # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (23 commits) MAINTAINERS: Add myself as maintainer of e500 machines docs/devel: Mention post_load hook restrictions where we document the hook tests/functional: Fix hash validation hw/mips: Build fw_cfg.c once tests/tcg/plugins: Remove remainder of the cris target block-backend: Remove deadcode hw/net/rocker: Remove unused rocker_fp_ports hw/pci: Remove unused pcie_chassis_find_slot replay: Remove unused replay_disable_events remote: Remove unused remote_iohub_finalize vhost: Remove unused vhost_dev_{load|save}_inflight ui/cursor: remove cursor_get_mono_image hw: Remove unused fw_cfg_init_io linux-user: Remove unused handle_vm86_fault hw/char: Remove unused serial_set_frequency hw/net/net_rx_pkt: Remove deadcode net: Remove deadcode q35: Remove unused mch_mcfg_base hw/xen: Remove deadcode MAINTAINERS: remove gensyscalls.sh from the linux-user section ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-03hw/arm: xenpvh: Enable PCI for ARM PVHEdgar E. Iglesias1-0/+14
Enable PCI support for the ARM Xen PVH machine. Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-03hw/xen: xenpvh: Add pci-intx-irq-base propertyEdgar E. Iglesias1-0/+36
Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-03hw/xen: xenpvh: Disable buffered IOREQs for ARMEdgar E. Iglesias3-1/+7
Add a way to enable/disable buffered IOREQs for PVH machines and disable them for ARM. ARM does not support buffered IOREQ's nor the legacy way to map IOREQ info pages. See the following for more details: https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=2fbd7e609e1803ac5e5c26e22aa8e4b5a6cddbb1 https://xenbits.xen.org/gitweb/?p=xen.git;a=blob;f=xen/arch/arm/ioreq.c;h=2e829d2e7f3760401b96fa7c930e2015fb1cf463;hb=HEAD#l138 Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-03hw/xen: Expose handle_bufioreq in xen_register_ioreqEdgar E. Iglesias3-40/+68
Expose handle_bufioreq in xen_register_ioreq(). This is to allow machines to enable or disable buffered ioreqs. No functional change since all callers still set it to HVM_IOREQSRV_BUFIOREQ_ATOMIC. Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-039p: remove 'proxy' filesystem backend driverPaolo Bonzini3-1381/+0
It has been deprecated since 8.1; remove it and suggest using the 'local' file system backend driver instead or virtiofsd. Acked-by: Greg Kurz <groug@kaod.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw/char: Extract serial-mmBernhard Beschow46-185/+222
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies more obvious and the code more tidy. The includes and the dependencies have been converted mechanically except in the hw/char directories which were updated manually. The result was compile-tested. Now, only hw/char makes direct use of TYPE_SERIAL: # grep -r -e "select SERIAL" | grep -v SERIAL_ hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL # grep -r -e "/serial\\.h" include/hw/char/serial-mm.h:#include "hw/char/serial.h" hw/char/serial-pci-multi.c:#include "hw/char/serial.h" hw/char/serial.c:#include "hw/char/serial.h" hw/char/serial-isa.c:#include "hw/char/serial.h" hw/char/serial-pci.c:#include "hw/char/serial.h" Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-4-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw/char/serial.h: Extract serial-isa.hBernhard Beschow8-6/+8
The includes where updated based on compile errors. Now, the inclusion of the header roughly matches Kconfig dependencies: # grep -r -e "select SERIAL_ISA" hw/ppc/Kconfig: select SERIAL_ISA hw/isa/Kconfig: select SERIAL_ISA hw/sparc64/Kconfig: select SERIAL_ISA hw/i386/Kconfig: select SERIAL_ISA hw/i386/Kconfig: select SERIAL_ISA # for serial_hds_isa_init() Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-3-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw: Remove unused inclusion of hw/char/serial.hBernhard Beschow4-4/+0
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-2-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw/mips: Build fw_cfg.c oncePhilippe Mathieu-Daudé1-1/+1
Nothing in fw_cfg.c requires target-specific knowledge, build it once for the 4 MIPS variants. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-10-03hw/net/rocker: Remove unused rocker_fp_portsDr. David Alan Gilbert2-6/+0
rocker_fp_ports hasn't been used since it was added back in 2015. Remove it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
generated by cgit v1.1 at 2024-10-19 19:10:15 +0000