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path: root/llvm/test/Transforms/LoopStrengthReduce/AArch64
AgeCommit message (Expand)AuthorFilesLines
2025-12-03[LSR] Make OptimizeLoopTermCond able to handle some non-cmp conditions (#165590)John Brawn1-0/+205
2025-12-02[LSR] Insert the transformed IV increment in the user block (#169515)John Brawn1-3/+1
2025-11-10[AArch64][SVE] Avoid movprfx by reusing register for _UNDEF pseudos. (#166926)Sander de Smalen1-3/+2
2025-10-30[LSR] Don't count conditional loads/store as enabling pre/post-index (#159573)John Brawn1-4/+140
2025-09-16[LSR] Add an addressing mode that considers all addressing modes (#158110)John Brawn1-0/+178
2025-08-01[LLVM][DAGCombiner] fold (shl (X * vscale(C0)), C1) -> (X * vscale(C0 << C1))...Paul Walker1-4/+4
2025-07-11[AArch64LoadStoreOpt] BaseReg update is searched also in CF successor (#145583)Sergey Shcherbinin1-2/+1
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David1-12/+14
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David1-14/+12
2025-06-16[LSR] Make canHoistIVInc allow non-integer types (#143707)John Brawn1-0/+189
2025-04-17[AArch64][SVE] Fold ADD+CNTB to INCB/DECB (#118280)Ricardo Jesus1-32/+33
2025-02-26[AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (#127837)Ricardo Jesus1-38/+29
2024-12-29Remove -print-lsr-output in favor of --stop-after=loop-reduceFangrui Song1-1/+1
2024-11-21[llvm] Remove `br i1 undef` from some regression tests [NFC] (#117112)Lee Wei1-36/+36
2024-07-24[LSR] Fix matching vscale immediates (#100080)Benjamin Maxwell1-8/+12
2024-07-23Precommit vscale-fixups.ll test (NFC)Benjamin Maxwell1-0/+47
2024-07-01[LSR] Recognize vscale-relative immediates (#88124)Graham Hunter1-0/+387
2024-06-06[AArch64] Override isLSRCostLess, take number of instructions into account (#...Graham Hunter1-2/+4
2023-08-21[AArch64] Update generic sched model to A510Harvin Iriawan3-14/+14
2023-07-13[LSR] Don't consider users of constant outside loopNikita Popov1-19/+14
2023-07-13[LSR] Add test variant with global variables (NFC)Nikita Popov1-2/+44
2023-07-12[LSR] Convert test to opaque pointers (NFC)Nikita Popov1-14/+17
2023-06-27[test] Replace aarch64-*-eabi with aarch64Fangrui Song1-1/+1
2023-06-23[LSR] Regenerate test checks (NFC)Nikita Popov1-5/+19
2023-06-19[LSR] Add test for for issue leading to revert of abfeda5af329b5.Florian Hahn1-0/+53
2023-05-25[CodeGen][ShrinkWrap] Enable PostShrinkWrap by defaultsgokhale1-3/+3
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta1-2/+2
2023-05-08Revert "[CodeGen][ShrinkWrap] Split restore point"Alan Zhao1-3/+3
2023-05-08[CodeGen][ShrinkWrap] Split restore pointsgokhale1-3/+3
2023-04-21Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`"Momchil Velikov1-3/+3
2023-04-20Revert "[AArch64] Fix incorrect `isLegalAddressingMode`"Momchil Velikov1-3/+3
2023-04-20[AArch64] Fix incorrect `isLegalAddressingMode`Momchil Velikov1-3/+3
2023-03-17[SCEVExpander] Always use scevgep as nameNikita Popov1-1/+1
2023-02-10[Reland][LSR] Hoist IVInc to loop header if its all uses are in the loop headerchenglin.bi1-6/+126
2023-01-18[AsmParser] Remove typed pointer auto-detectionNikita Popov1-1/+1
2023-01-11Revert "[LSR] Hoist IVInc to loop header if its all uses are in the loop header"chenglin.bi1-73/+6
2023-01-10[LSR] Hoist IVInc to loop header if its all uses are in the loop headerchenglin.bi1-6/+73
2023-01-05[Transforms] Convert some tests to opaque pointers (NFC)Nikita Popov7-121/+112
2022-12-20Revert "Reland "[SimplifyCFG] `FoldBranchToCommonDest()`: deal with mismatche...Roman Lebedev1-22/+20
2022-12-17Reland "[SimplifyCFG] `FoldBranchToCommonDest()`: deal with mismatched IV's i...Roman Lebedev1-20/+22
2022-12-16Revert "[SimplifyCFG] `FoldBranchToCommonDest()`: deal with mismatched IV's i...Alexander Kornienko1-22/+20
2022-12-12[SimplifyCFG] `FoldBranchToCommonDest()`: deal with mismatched IV's in PHI's ...Roman Lebedev1-20/+22
2022-11-25[LSR] precommit test for D138636; NFCchenglin.bi1-0/+52
2022-06-15[LSR] Add test for LoopStrenghtReduce for Ldp; NFCchenglin.bi1-0/+75
2021-10-09[AArch64] Make -mcpu=generic schedule for an in-order coreDavid Green2-7/+7
2021-10-06[AArch64] Regenerate even more testsDavid Green1-0/+1
2021-08-03[AArch64] Prefer fmov over orr v.16b when copying f32/f64David Green1-3/+2
2021-08-03[AArch64InstPrinter] Change printAddSubImm to comment imm value when shiftedJason Molenda2-7/+7
2021-04-15[LSR] Fix for pre-indexed generated constant offsetStelios Ioannou1-0/+53
2020-09-10Mark FMOV constant materialization as being as cheap as a move.Owen Anderson1-7/+5
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