aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/Transforms/LoopStrengthReduce
AgeCommit message (Expand)AuthorFilesLines
3 days[LLVM][DAGCombiner] fold (shl (X * vscale(C0)), C1) -> (X * vscale(C0 << C1))...Paul Walker1-4/+4
2025-07-18[LSR] Do not consider uses in lifetime intrinsics (#149492)Nikita Popov1-0/+59
2025-07-14[DebugInfo][LoopStrengthReduce] Salvage the debug value of the dead cmp instr...Shan Huang1-1/+12
2025-07-11Revert "[LSR] Regenerate test checks (NFC)"Nikita Popov1-209/+112
2025-07-11[LSR] Regenerate test checks (NFC)Nikita Popov1-112/+209
2025-07-11[AArch64LoadStoreOpt] BaseReg update is searched also in CF successor (#145583)Sergey Shcherbinin1-2/+1
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David2-19/+25
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David2-25/+19
2025-06-16[LSR] Make canHoistIVInc allow non-integer types (#143707)John Brawn1-0/+189
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song1-16/+12
2025-04-30[AMDGPU] Remove explicit datalayout from tests where not neededAlexander Richardson5-12/+0
2025-04-17[AArch64][SVE] Fold ADD+CNTB to INCB/DECB (#118280)Ricardo Jesus1-32/+33
2025-03-29MIPS: Set EnableLoopTermFold (#133454)YunQiang Su2-29/+58
2025-03-28Revert "MIPS: Set EnableLoopTermFold (#133378)"Weaver1-56/+29
2025-03-28MIPS: Set EnableLoopTermFold (#133378)YunQiang Su1-29/+56
2025-03-26MIPS: Implements MipsTTIImpl::isLSRCostLess using Insns as first (#133068)YunQiang Su1-0/+72
2025-03-14[RemoveDIs] Remove "try-debuginfo-iterators..." test flags (#130298)Jeremy Morse15-15/+0
2025-02-26[AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (#127837)Ricardo Jesus1-38/+29
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov1-2/+2
2025-01-29[IR] Convert from nocapture to captures(none) (#123181)Nikita Popov5-7/+7
2025-01-07[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)Alex MacLean1-3/+1
2024-12-29Remove -print-lsr-output in favor of --stop-after=loop-reduceFangrui Song1-1/+1
2024-11-21[llvm] Remove `br i1 undef` from some regression tests [NFC] (#117112)Lee Wei29-158/+158
2024-11-11[SCEVExpander] Don't try to reuse SCEVUnknown values (#115141)Nikita Popov2-5/+3
2024-11-07[SCEV] Disallow simplifying phi(undef, X) to X (#115109)Yingwei Zheng1-8/+8
2024-10-17[llvm][LSR] Fix where invariant on ScaledReg & Scale is violated (#112576)Youngsuk Kim1-0/+30
2024-10-03[DebugInfo][LSR] Fix assertion failure salvaging IV with offset > 64 bits wid...Orlando Cazalet-Hyams1-0/+40
2024-10-02[X86] Don't request 0x90 nop filling in p2align directives (#110134)Jeremy Morse4-16/+16
2024-10-02[SCEVExpander] Preserve gep nuw during expansion (#102133)Nikita Popov3-3/+3
2024-10-01[SCEVExpander] Clear flags when reusing GEP (#109293)Nikita Popov2-5/+5
2024-09-19[LSR] Regenerate test checks (NFC)Nikita Popov2-17/+59
2024-09-09Reland "[LSR] Do not create duplicated PHI nodes while preserving LCSSA form"...Sergey Kachkov6-33/+35
2024-09-09[LSR][NFC] Add pre-commit testSergey Kachkov1-0/+85
2024-09-06Revert "[LSR] Do not create duplicated PHI nodes while preserving LCSSA form"...dyung6-146/+29
2024-09-06[LSR] Do not create duplicated PHI nodes while preserving LCSSA form (#107380)Sergey Kachkov6-29/+146
2024-08-17[LSR] Split the -lsr-term-fold transformation into it's own pass (#104234)Philip Reames5-6/+7
2024-07-24[LSR] Fix matching vscale immediates (#100080)Benjamin Maxwell1-8/+12
2024-07-23Precommit vscale-fixups.ll test (NFC)Benjamin Maxwell1-0/+47
2024-07-15[RISCV] Copy AVLs whose LiveIntervals aren't extendable in insertVSETVLI (#98...Luke Lau1-1/+0
2024-07-15[DebugInfo][LoopStrengthReduce] Fix missing debug location updates (#97519)Shan Huang1-0/+59
2024-07-10Revert "[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default"...Alex Bradbury4-32/+55
2024-07-10[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default (#89927)Alex Bradbury4-55/+32
2024-07-05[RISCV] Don't forward AVL in VSETVLIInfo if it would clobber other definition...Luke Lau1-0/+1
2024-07-01[LSR] Recognize vscale-relative immediates (#88124)Graham Hunter1-0/+387
2024-06-23[RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (#96200)Luke Lau1-1/+0
2024-06-20[IR] Remove support for shl constant expressions (#96037)Nikita Popov1-3/+3
2024-06-19[SCEVExpander] Recognize urem idiom during expansion (#96005)Philip Reames1-6/+2
2024-06-14 [RemoveDIs] Print IR with debug records by default (#91724)Stephen Tozer13-31/+31
2024-06-06[AArch64] Override isLSRCostLess, take number of instructions into account (#...Graham Hunter1-2/+4
2024-06-05[RISCV][test] Precommit LSR test that partially motivates #89927Alex Bradbury1-0/+109
generated by cgit v1.1 at 2025-08-04 16:29:33 +0000