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52 min.[AMDGPU] Add dot4 fp8/bf8 instructions for gfx1170 (#180516)Mirko Brkušanin11-2/+798
67 min.[LV] Handle partial sub-reductions with sub in middle block. (#178919)Sander de Smalen3-24/+102
82 min.[CoroSplit][DebugInfo] Fix scope of continuation funclets (#180523)Felipe de Azevedo Piovezan1-0/+69
93 min.[AMDGPU] Add legalization rules for atomicrmw max/min ops (#180502)Anshil Gandhi5-11/+1597
102 min.[SCEV] Add ptrtoaddr tests with external state/unstable addrspaces.Florian Hahn1-1/+76
114 min.[AArch64] Add support for intent to read prefetch intrinsic (#179709)Kerry McLaughlin2-1/+21
2 hoursReland "[LV] Support conditional scalar assignments of masked operations" (#1...Benjamin Maxwell3-9/+1244
2 hoursInstCombine: Use SimplifyDemandedFPClass on fmul (#177490)Matt Arsenault18-68/+66
3 hours[MemorySSA] Relax clobbering checks for calls to consider writes only (#179721)CarolineConcatto1-0/+13
3 hours[OCaml] Remove global_context (#180533)Nikita Popov13-27/+42
3 hours[SDAG] Implement missing legalization for `ISD::VECTOR_FIND_LAST_ACTIVE` (#18...Benjamin Maxwell3-18/+333
3 hours[VPlan] Simplify true && x -> x (#179426)Mel Chen2-9/+6
4 hours[AMDGPU] Add intrinsic exposing s_alloc_vgpr (#163951)Diana Picus2-0/+132
4 hours[RISCV] Enable select optimization by default (#178394)Pengcheng Wang3-15/+32
5 hours[NewPM] Port x86-global-base-reg (#180119)Kyungtak Woo1-0/+4
6 hours[RISCV] Remove redundant czero in multi-word comparisons (#180485)Craig Topper2-74/+49
7 hours[DebugInfo] Fix an assertion in DWARFTypePrinter (#178986)Peter Rong1-3283/+3406
10 hoursAMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)vangthao952-181/+414
10 hoursLowerTypeTests: Optimize two-phase check used by llvm.cond.loop.Peter Collingbourne1-0/+45
10 hours[RISCV] Generate 8alt/16alt version error message for zvfofp8min (#180450)Jim Lin2-0/+11
10 hours[DebugInfo] Update test to sync with cross-project-tests (#180655)Peter Rong1-5362/+5490
11 hours[SPIRV] Add handling for `uinc_wrap` and `udec_wrap` atomics (#179114)Lleu Yang3-0/+78
12 hoursRevert "[msan] Switch switch() from strict handling to (icmp eq)-style handli...Andrew Lazarev1-20/+5
12 hours[SPIR-V] Emit ceil(Bitwidth / 32) words during OpConstant creation (#180218)Dmitry Sidorov1-0/+30
13 hours[win][aarch64] The Windows Control Flow Guard Check function also preserves X...Daniel Paoliello1-21/+58
13 hours[LV] Add FindLast tests where IV-based expression could be sunk. (NFC)Florian Hahn1-0/+934
13 hours[RISCV] Add missing instruction tests to rv64p-valid.s. NFC (#180316)Craig Topper1-0/+12
13 hours[VPlan] Auto-generate CHECKs in some VPlan printing tests.Florian Hahn4-150/+251
13 hours[LV] Add additional tests for reductions with intermediate stores. (NFC)Florian Hahn2-3/+160
13 hours[RISCV] Combine shuffle of shuffles to a single shuffle (#178095)Ryan Buchner2-6/+444
14 hours[SPIRV] Implement lowering for HLSL Texture2D sampling intrinsics (#179312)Steven Perron11-0/+550
14 hours[VPlan] Simplify single-entry VPWidenPHIRecipe.Florian Hahn7-25/+16
15 hours[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity ...Alexey Merzlyakov1-0/+166
16 hours[Hexagon] Fix encoding of packets with fixups followed by alignment (#179168)Brian Cain1-0/+49
16 hours[ForceFunctionAttrs] Fix handling of `alwaysinline` and `noinline` attributes...Justin Fargnoli1-9/+36
17 hours[AMDGPU] Enable sinking of free vector ops that will be folded into their use...Gheorghe-Teodor Bercea2-12/+184
18 hours[SPARC] Add TTI implementation for getPopcntSupport (#178843)Koakuma2-0/+327
18 hours[llubi] Add initial support for llubi (#180022)Yingwei Zheng5-0/+33
18 hours[AArch64] Add support for B and H loads/stores in LoadStoreOptimizer (#180535)John Brawn1-0/+250
19 hoursAMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sffbh (#180099)vangthao951-19/+29
19 hoursAMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)vangthao954-0/+1772
19 hours[MIParser] - Add support for MMRAs (#180320)Ryan Mitchell2-0/+74
19 hours[RISCV] Combine ADDD+WMULSU to WMACCSU (#180454)Craig Topper1-0/+28
20 hours[X86] Fold expand(splat,passthrough,mask) -> select(splat,passthrough,mask) (...Simon Pilgrim1-12/+9
20 hours[InstCombine] Support minimumnum/maximumnum (#180529)Nikita Popov2-0/+826
20 hours[SPIR-V] initial support for @llvm.structured.gep (#178668)Nathan Gauër7-0/+416
20 hours[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)Anshil Gandhi8-46/+479
21 hoursReland "[LoopVectorize] Support vectorization of overflow intrinsics" (#180526)Vishruth Thimmaiah3-17/+560
21 hours[IVDesc] Check loop-preheader for loop-legality when pass-remarks enabled (#1...hanbeom1-0/+24
22 hours[AMDGPU] Fix instruction size for 64-bit literal constant operands (#180387)Shilei Tian1-2/+10
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