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path: root/llvm/test/CodeGen/RISCV/half-convert.ll
AgeCommit message (Expand)AuthorFilesLines
40 hours[DAG] canCreateUndefOrPoison - add FP_EXTEND (#152249)Chaitanya Koparkar1-52/+56
2025-07-21[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)Alex Bradbury1-39/+21
2025-06-02[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w)...Alex Bradbury1-29/+29
2025-03-28[RISCV][MC] Enable printing of zext.b alias (#133502)Alex Bradbury1-2/+2
2025-02-13Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#12...Philip Reames1-326/+326
2025-02-12[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)Philip Reames1-326/+326
2024-12-10[LegalizeTypes][RISCV][X86] Legalize FP_ROUND to libcall in SoftPromoteHalfRe...Craig Topper1-0/+808
2024-11-15[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)Pengcheng Wang1-473/+473
2024-09-26[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)Craig Topper1-0/+12
2024-09-12[LegalizeIntegerTypes] Simplify ExpandIntRes_FP_TO_XINT when operand needs to...Craig Topper1-4/+0
2024-09-06[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)Craig Topper1-124/+100
2024-09-05[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)Craig Topper1-116/+116
2024-09-03[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that e...Craig Topper1-12/+12
2024-09-03[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)Craig Topper1-45/+30
2024-08-08[RISCV] Add some Zfinx instructions to hasAllNBitUsers.Craig Topper1-10/+6
2024-04-29Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison ...Bjorn Pettersson1-149/+119
2024-04-29Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)...David Spickett1-119/+149
2024-04-26[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)Bjorn Pettersson1-149/+119
2024-04-15[mi-sched] Suppress register pressure with i64. (#88256)laichunfeng1-66/+66
2024-03-25[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuara...Craig Topper1-31/+26
2024-03-20[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and G...Craig Topper1-42/+8
2024-03-08[SelectionDAG] Allow FREEZE to be hoisted before FP SETCC. (#84358)Craig Topper1-38/+19
2024-03-07[RISCV] Insert a freeze before converting select to AND/OR. (#84232)Craig Topper1-158/+212
2024-01-07[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)Fangrui Song1-437/+437
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-60/+60
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-60/+60
2023-10-06[RISCV] Strip W suffix from ADDIW (#68425)Philip Reames1-23/+23
2023-07-24[RISCV] Remove unused check prefixes for tests. NFCJim Lin1-9/+4
2023-07-05[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))Craig Topper1-50/+0
2023-06-30[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcallAlex Bradbury1-28/+71
2023-06-30[RISCV][test] Add additional RUN lines to half-convert.ll in preparation for ...Alex Bradbury1-0/+2267
2023-05-30[RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floa...Alex Bradbury1-14/+0
2023-05-25[RISCV][CodeGen] Support Zdinx on RV32 codegenShao-Ce SUN1-14/+20
2023-05-12[RISCV][CodeGen] Support Zhinx and ZhinxminQihan Cai1-0/+2547
2023-04-29[TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT.Craig Topper1-331/+286
2023-03-27[RISCV] Move compressible registers to the beginning of the FP allocation order.Craig Topper1-396/+396
2023-03-16[RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1)LiaoChunyu1-28/+14
2023-02-03[RISCV] Don't use constantpool for floating-point value if the value can be e...Han-Kuan Chen1-202/+202
2022-12-19[RISCV] Convert some tests to opaque pointers (NFC)Nikita Popov1-9/+9
2022-12-14[RISCV][CodeGen][SelectionDAG] Recursively check hasAllNBitUsers for logical ...Nitin John Raj1-9/+9
2022-12-06[RISCV] Codegen support for Zfhmin.Monk Chiang1-0/+796
2022-12-01[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.Craig Topper1-2/+2
2022-11-25[RISCV] Use register allocation hints to improve use of compressed instructions.Craig Topper1-44/+40
2022-10-18[RISCV] Optimize SELECT_CC when the true value of select is ConstantLiaoChunyu1-143/+140
2022-10-13[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelectCraig Topper1-128/+107
2022-10-12[RISCV] Use branchless form for selects with 0 in either armPhilip Reames1-425/+377
2022-10-06[RISCV] Use branchless form for selects with -1 in either armPhilip Reames1-243/+164
2022-09-13[RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering on RV64.Craig Topper1-16/+42
2022-09-12[RISCV] Add test cases with result of fp_to_s/uint_sat sign/zero-extended fro...Craig Topper1-0/+237
2022-08-01[RISCV] Explicitly select second operand of branch condition to X0.Craig Topper1-164/+146
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