| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 7 hours | [RISCV] Combine ADDD with UMUL_LOHI/SMUL_LOHI into WMACCU/WMACC (#180383)HEADmain | Craig Topper | 1 | -0/+76 |
| 8 hours | [RISCV] Add support for forming WMULSU during type legalization. (#180331) | Craig Topper | 1 | -2/+27 |
| 2 days | [RISCV] Use addd/subd for i64 add/sub for RV32+P. (#180129) | Craig Topper | 1 | -9/+25 |
| 3 days | [RISCV][llvm] Support INSERT_VECTOR_ELT codegen for P extension (#179471) | Brandon Wu | 2 | -10/+144 |
| 3 days | [RISCV] Add wmul(u) codegen for RV32+P (#180032) | Craig Topper | 1 | -1/+51 |
| 3 days | [GlobalISel] Add SVE support for alloca (#178976) | Jameson Nash | 2 | -11/+15 |
| 4 days | [RISCV] Fold vmerge into op with undef passthru by using vmerge's vl (#179862) | Luke Lau | 2 | -0/+57 |
| 4 days | [RISCV] Remove redundant vand.vi with fpto*i to i1 (#179876) | Luke Lau | 2 | -116/+42 |
| 4 days | [RISCV] Remove trivial constant from fixed-vectors-vminu-vp.ll test. NFC (#17... | Luke Lau | 1 | -23/+54 |
| 4 days | [RISCV] Correct lowering of ISD::SETGE/SETULE/SETLE/SETUGE in lowerVPSetCCMas... | Craig Topper | 2 | -44/+44 |
| 5 days | [RISCV] Add macro fusion support for spacemit-x100 (#178594) | Mark Zhuang | 7 | -0/+495 |
| 5 days | [RISCV] Run VLOptimizer right after ISel (#179377) | Min-Yih Hsu | 78 | -413/+428 |
| 5 days | [RISCV] Enable SelectCompressOpt with HasStdExtZca. (#179601) | Craig Topper | 1 | -0/+3 |
| 5 days | [RISCV] Add isel patterns to form vwsll.vx/vi when the LHS is an any_extend. ... | Craig Topper | 1 | -0/+78 |
| 5 days | [RISCV] Print MIR comments for AVL and VEC_RM operands (#179542) | Min-Yih Hsu | 53 | -1211/+1211 |
| 5 days | [llvm][RISCV] precommit test update via UTC (#179508) | Paul Kirth | 1 | -71/+107 |
| 6 days | [LegalizeTypes] Don't promote operands to VP extends (#179475) | Luke Lau | 25 | -88/+87 |
| 6 days | [RISC-V][Mach-O] Add codegen support for Mach-O object format. (#178263) | Francesco Petrogalli | 1 | -0/+96 |
| 8 days | [SDAG] Check for `nsz` in DAG.canIgnoreSignBitOfZero() (#178905) | Benjamin Maxwell | 1 | -13/+9 |
| 9 days | [DAG] Reland: Enable bitcast STLF for Constant/Undef (#178890) | 陈子昂 | 1 | -0/+67 |
| 10 days | Revert "[DAG] Enable bitcast STLF for Constant/Undef" (#178872) | Alex Bradbury | 1 | -12/+0 |
| 10 days | [DAG] Enable bitcast STLF for Constant/Undef (#172523) | 陈子昂 | 1 | -0/+12 |
| 10 days | [RISCV] Add isel pattern (setlt (shl X, 32), 0) -> srliw. (#178765) | Craig Topper | 2 | -12/+8 |
| 10 days | [RISCV] Support ISD::CLMUL/CLMULH for i64 scalable vectors with Zvbc. (#178340) | Craig Topper | 2 | -4816/+69885 |
| 10 days | [InlineSpiller] Hoist spills only when all of its subranges are available (#1... | Min-Yih Hsu | 1 | -0/+146 |
| 10 days | [GlobalISel] Rewrite binop_left_to_zero using MIR Patterns (#177924) | Osman Yasar | 2 | -40/+156 |
| 11 days | Revert "[RISCV] Support RISCV BitInt larger than 128 (#175515)" (#178311) | Craig Topper | 2 | -7567/+849 |
| 11 days | [RISCV] Add ISEL pattern to convert add (shl -1, X), Y to sub Y, (bset zero, ... | Sudharsan Veeravalli | 2 | -16/+52 |
| 11 days | [RISCV] Update P extension to 019. (#178031) | Craig Topper | 1 | -1/+1 |
| 11 days | [DAG] SimplifyDemandedBits - ICMP_SLT(X,0) - only sign mask of X is required ... | Anikesh Parashar | 2 | -9/+12 |
| 12 days | [RISCV] Add signext attribute to llvm.clmul test caes in rv64zbc(-zbkc)-intri... | Craig Topper | 2 | -3/+5 |
| 12 days | [RISCV][test] Simplify a test. (#178052) | Mikhail Gudim | 1 | -2/+2 |
| 13 days | [RISCV] Reorder some check-prefixes in a way that makes the update script wor... | Craig Topper | 2 | -10/+10 |
| 13 days | [RISCV] Remove 'implicit $vl' from PseudoVMV_X_S in emergency-slot.mir. NFC (... | Craig Topper | 1 | -2/+2 |
| 13 days | [RISCV] Support select optimization | Pengcheng Wang | 2 | -0/+959 |
| 13 days | [RISCV] Replace riscv.clmul intrinsic with llvm.clmul (#178092) | Craig Topper | 2 | -0/+3 |
| 13 days | [RISC-V] Fix outliner candidate analysis (#177126) | Nemanja Ivanovic | 1 | -0/+354 |
| 14 days | [RISCV] Run combineOrToBitfieldInsert after DAG legalize (#177830) | Sudharsan Veeravalli | 1 | -0/+22 |
| 14 days | [RISC-V][MC] Introduce RVY extension feature | Alexander Richardson | 2 | -0/+3 |
| 14 days | [NFC] Fix "FIMXE" typos to "FIXME" (#177895) | Fady Farag | 1 | -1/+1 |
| 2026-01-23 | [RISCV] Select (clmul (zext_inreg X, i32), (zext_inreg X, i32)) as (clmulh (s... | Craig Topper | 2 | -6/+2 |
| 2026-01-23 | [profcheck] Fix profle metatdata propagation for Large Integer operations (#1... | Jin Huang | 1 | -531/+530 |
| 2026-01-23 | [DAG] Add basic folds for CLMUL nodes (#176961) | Vishruth Thimmaiah | 1 | -0/+85 |
| 2026-01-22 | [SelectionDAG] Add very basic computeKnownBits support for ISD::CLMUL. (#177445) | Craig Topper | 2 | -127/+61 |
| 2026-01-22 | [RISCV] Replace RISCVISD::CLMUL* with ISD::CLMUL*. (#177386) | Craig Topper | 4 | -0/+116 |
| 2026-01-22 | [RISCV]Remove experimental from Zalasr (#177120) | Liao Chunyu | 7 | -24/+24 |
| 2026-01-21 | [RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them... | Craig Topper | 10 | -35/+106 |
| 2026-01-21 | [IR] Allow non-constant offsets in @llvm.vector.splice.{left,right} (#174693) | Luke Lau | 1 | -0/+80 |
| 2026-01-21 | [RISCV][llvm] Support setcc codegen for zvfbfa (#176866) | Brandon Wu | 2 | -632/+1530 |
| 2026-01-21 | [RISCV][llvm] Support [v]select codegen for zvfbfa (#176865) | Brandon Wu | 2 | -4/+126 |
