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path: root/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
AgeCommit message (Expand)AuthorFilesLines
12 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-2/+2
2025-05-11[AMDGPU] Move kernarg preload logic to separate pass (#130434)Austin Kerbow1-4/+4
2025-04-24AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)Matt Arsenault1-2/+0
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov1-6/+6
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-194/+194
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-194/+194
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-194/+194
2024-10-08[AMDGPU] Include WWM register spill into BB Prolog (#111496)Christudasan Devadasan1-6/+6
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan1-288/+206
2024-09-14[AMDGPU] Avoid unneeded waitcounts before spill stores (#108303)Stanislav Mekhanoshin1-2/+2
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad1-326/+334
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson1-264/+240
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-102/+164
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-164/+102
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-102/+164
2024-04-01[AMDGPU] Use glue for convergence tokens at call-like operations (#86766)Sameer Sahasrabuddhe1-4/+0
2024-03-06[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)Emma Pilkington1-1/+1
2024-03-06Restore "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe1-0/+4
2024-03-04Revert "Restore "Implement convergence control in MIR using SelectionDAG (#71...Mitch Phillips1-4/+0
2024-03-04Restore "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe1-0/+4
2024-02-21Revert "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe1-4/+0
2024-02-21Implement convergence control in MIR using SelectionDAG (#71785)Sameer Sahasrabuddhe1-0/+4
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus1-44/+44
2023-12-15[AMDGPU][NFC] Check more autogenerated llc tests for COV5 (#75219)Saiyedul Islam1-108/+115
2023-11-10[AMDGPU] si-wqm: Skip only LiveMask COPYDiana Picus1-12/+12
2023-11-06Reapply [AMDGPU] Generate wwm-reserved.ll (NFC)Carl Ritson1-147/+1492
2023-11-02Revert "[AMDGPU] Generate wwm-reserved.ll (NFC)"Nico Weber1-1492/+147
2023-11-02[AMDGPU] Generate wwm-reserved.ll (NFC)Carl Ritson1-147/+1492
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault1-3/+5
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka1-5/+3
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-3/+5
2023-06-08AMDGPU: Don't run AMDGPUAttributor with -O0Matt Arsenault1-12/+16
2023-06-05[AMDGPU] Add buffer intrinsics that take resources as pointersKrzysztof Drewniak1-32/+36
2022-02-18[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Jay Foad1-18/+18
2022-02-06AMDGPU: Don't clobber source register for V_SET_INACTIVE_*Ruiling Song1-12/+6
2021-11-24[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32Jay Foad1-8/+8
2021-09-22[AMDGPU] Divergence-driven instruction selection for mul i32Jay Foad1-4/+4
2021-07-15[AMDGPU] Refine -O0 and -O1 passes.Stanislav Mekhanoshin1-14/+28
2021-03-03[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwmPiotr Sobczak1-0/+191
2020-10-28[AMDGPU] Fix insert of SIPreAllocateWWMRegs in FastRegAllocCarl Ritson1-15/+12
2020-10-27[AMDGPU] Move WQM Pass after MI SchedulerCarl Ritson1-7/+8
2020-09-30Reapply "RegAllocFast: Rewrite and improve"Matt Arsenault1-16/+25
2020-09-22Revert "Reapply Revert "RegAllocFast: Rewrite and improve""Muhammad Omair Javaid1-25/+16
2020-09-21Reapply Revert "RegAllocFast: Rewrite and improve"Matt Arsenault1-16/+25
2020-09-18Temporarily Revert "RegAllocFast: Rewrite and improve"Eric Christopher1-25/+16
2020-09-18RegAllocFast: Rewrite and improveMatt Arsenault1-16/+25
2020-09-18Reapply "RegAllocFast: Record internal state based on register units"Matt Arsenault1-4/+4
2020-09-15Revert "RegAllocFast: Record internal state based on register units"Hans Wennborg1-4/+4
2020-06-19[AMDGPU] Add some missing -LABEL checksJay Foad1-0/+7
2020-06-03RegAllocFast: Record internal state based on register unitsMatt Arsenault1-4/+4
generated by cgit v1.1 at 2025-08-04 21:08:11 +0000