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path: root/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
AgeCommit message (Expand)AuthorFilesLines
10 days[AMDGPU] Allocate AVRegClass last (#146606)Jeffrey Byrnes1-16/+14
12 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-5/+5
2025-04-23[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#13...Brox Chen1-524/+1165
2025-03-12AMDGPU: Replace tests using undef in shufflevector with poison (#130899)Matt Arsenault1-51/+51
2025-03-12AMDGPU: Replace insertelement poison with insertelement undef (#130896)Matt Arsenault1-3/+3
2025-02-13[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)Fabian Ritter1-970/+778
2025-01-23AMDGPU: Make vector_shuffle legal for v2i32 with v_pk_mov_b32 (#123684)Matt Arsenault1-48/+48
2025-01-09AMDGPU: Custom lower bf16 shuffles (#122252)Matt Arsenault1-906/+1696
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-23/+23
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-23/+23
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-23/+23
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin1-6/+0
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-43/+47
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-47/+43
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-43/+47
2024-02-21[TargetLowering] Be more efficient in fp -> bf16 NaN conversionsDavid Majnemer1-41/+31
2024-02-21[TargetLowering] Correctly yield NaN from FP_TO_BF16David Majnemer1-10/+10
2024-02-21Correctly round FP -> BF16 when SDAG expands such nodes (#82399)David Majnemer1-77/+216
2024-01-05AMDGPU: Make v4bf16 a legal type (#76217)Matt Arsenault1-166/+233
2024-01-04AMDGPU: Make bf16/v2bf16 legal types (#76215)Matt Arsenault1-592/+258
2023-12-22AMDGPU: Add a few more bfloat codegen testsMatt Arsenault1-24/+2371
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad1-0/+2
2023-07-04[AMDGPU] Do not wait for vscnt on function entry and returnJay Foad1-166/+0
2023-01-15DAG: Avoid stack lowering if bitcast has an illegal vector result typeMatt Arsenault1-9/+3
2023-01-11AMDGPU/SIInsertWait: Skip dummy tied sourceRuiling Song1-3/+1
2023-01-09[AMDGPU] Cast sub-dword elements to i32 in concat_vectorsStanislav Mekhanoshin1-39/+13
2023-01-09[AMDGPU] More tests for vector_shuffle.packed.ll. NFC.Stanislav Mekhanoshin1-0/+644
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov1-180/+180
2022-11-23[AMDGPU][InsertWaits] No wait for WAW for global/scratch_loadRuiling Song1-4/+1
2022-10-03[AMDGPU] Use V_PERM to match buildvectors when inputs are not canonicalized (...jeff1-254/+480
2022-07-08[AMDGPU] Add GFX11 test coverageJay Foad1-0/+574
2022-05-18[AMDGPU] Aggressively fold immediates in SIShrinkInstructionsJay Foad1-6/+5
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad1-7/+6
2021-12-23[AMDGPU] Select build_vector DAG nodes according to the divergencealex-t1-26/+26
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-17/+16
2021-06-24[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTsCarl Ritson1-6/+6
2021-04-26[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impactsBaptiste Saleil1-24/+26
2021-03-29[AMDGPU] Extend gfx10 test coverage. NFC.Petar Avramovic1-0/+579
2021-02-26AMDGPU: Use kill instruction to hint soft clause live rangesMatt Arsenault1-8/+12
2021-01-26[AMDGPU] Update subtarget features for new target ID supportAustin Kerbow1-108/+140
2020-11-16AMDGPU: Select global saddr mode from SGPR pointerMatt Arsenault1-8/+7
2020-09-23Revert "[AMDGPU] Insert waitcnt after returning from call"Sebastian Neubauer1-0/+24
2020-09-23[AMDGPU] Insert waitcnt after returning from callSebastian Neubauer1-24/+0
2020-08-17AMDGPU: Match global saddr addressing modeMatt Arsenault1-17/+8
2020-07-17[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristicsJay Foad1-6/+6
2020-02-28[AMDGPU] Remove dubious logic in bidirectional list schedulerJay Foad1-14/+13
2020-02-10[SelectionDAG] Optimize build_vector of truncates and shiftsSebastian Neubauer1-14/+7
2020-01-24[AMDGPU] Allow narrowing muti-dword loadsStanislav Mekhanoshin1-5/+28
2020-01-24Allow combining of extract_subvector to extract elementStanislav Mekhanoshin1-64/+55
2019-12-17[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtrJay Foad1-89/+89
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