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path: root/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
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11 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-4/+4
2025-04-30[AMDGPU] Fix undefined scc register in successor block of SI_KILL terminators...mssefat1-0/+159
2025-03-24[AMDGCN][SIWholeQuadMode] Rework splitBlock/lowerKillI1/lowerKillF32 to handl...Juan Manuel Martinez Caamaño1-8/+4
2025-03-17AMDGPU: Migrate more tests away from undef (#131314)Matt Arsenault1-6/+15
2025-03-13AMDGPU: Replace some float undef test uses with poison (#131090)Matt Arsenault1-1/+1
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic1-2/+0
2025-03-13AMDGPU: Replace <8 x i32> undef uses in tests with poison (#130903)Matt Arsenault1-2/+2
2025-03-13AMDGPU: Replace <4 x i32> undef uses in tests with poison (#130902)Matt Arsenault1-2/+2
2025-03-13AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)Matt Arsenault1-7/+7
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata1-0/+2
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic1-2/+0
2025-03-08AMDGPU: Replace undef phi inputs with poison in tests (#130267)Matt Arsenault1-1/+1
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov1-1/+1
2025-01-14[AMDGPU] Fix computed kill mask (#122736)Piotr Sobczak1-4/+4
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin1-6/+0
2024-09-23AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)Matt Arsenault1-1/+1
2024-07-26[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC)...Changpeng Fang1-2/+2
2024-07-03[test] Remove immarg parameter attribute from calls (#97432)Jay Foad1-2/+2
2024-04-04[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)Jay Foad1-4/+0
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-4/+4
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad1-0/+5
2023-07-04[AMDGPU] Do not wait for vscnt on function entry and returnJay Foad1-26/+11
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov1-7/+7
2022-11-29[AMDGPU] Unify uniform return and divergent unreachable blocksBrendon Cahoon1-53/+44
2022-09-28AMDGPU: Make various vector undefs legalMatt Arsenault1-88/+25
2022-08-09[AMDGPU] Unify unreachable intrinsicsYaxun (Sam) Liu1-44/+53
2022-07-21[AMDGPU] Pre-sink IR input for some testsJay Foad1-1/+1
2022-07-08[AMDGPU] Add GFX11 test coverageJay Foad1-0/+457
2022-02-25[AMDGPU] Extend pre-emit peephole to redundantly masked VCCCarl Ritson1-6/+0
2022-01-21[AMDGPU] Remove lz and nomip combine from codegenSebastian Neubauer1-3/+6
2022-01-18[MachineSink] Allow sinking of constant or ignorable physreg usesVang Thao1-6/+12
2021-11-20[AMDGPU] Do not generate ELF symbols for the local branch target labelsRamNalamothu1-212/+212
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash1-86/+175
2021-08-25[AMDGPU] Divergence-driven compare operations instruction selectionalex-t1-3/+6
2021-08-10AMDGPU: Add alloc priority to global rangesMatt Arsenault1-21/+21
2021-06-21[AMDGPU] Add Optimize VGPR LiveRange Pass.Ruiling Song1-0/+6
2021-03-23[AMDGPU] Use non-compressed exports in a test. NFC.Jay Foad1-11/+10
2021-03-20[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeepholeCarl Ritson1-6/+12
2021-02-17[AMDGPU] Add implicit vcc_lo on S_CBRANCH_VCCNZ in wave32Piotr Sobczak1-486/+870
2021-02-11[AMDGPU] Move kill lowering to WQM pass and add live mask trackingCarl Ritson1-281/+296
2021-02-08[AMDGPU] Generate test checks and add GFX10 test coverageJay Foad1-256/+767
2021-02-03[AMDGPU] Added -mcpu to couple more tests. NFC.Stanislav Mekhanoshin1-1/+1
2021-01-02[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}...Roman Lebedev1-1/+1
2021-01-02[NFC][CodeGen][Tests] Mark all tests that fail to preserve DomTree for Simpli...Roman Lebedev1-1/+1
2020-07-03[AMDGPU] Insert PS early exit at end of control flowCarl Ritson1-1/+5
2020-07-03Revert "[AMDGPU] Insert PS early exit at end of control flow"Carl Ritson1-5/+1
2020-07-03[AMDGPU] Insert PS early exit at end of control flowCarl Ritson1-1/+5
2020-07-03[AMDGPU] Unify early PS termination blocksCarl Ritson1-38/+90
2020-06-02AMDGPU: Don't run mode switches with exec 0Matt Arsenault1-0/+20
2020-02-26AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill ...Nicolai Hähnle1-24/+42
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