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path: root/llvm/test/CodeGen/AMDGPU/shl.ll
AgeCommit message (Expand)AuthorFilesLines
2 days[DAG] Always use stack to promote bitcast when the source is vector (#151065)Min-Yih Hsu1-13/+46
13 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-3/+3
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song1-5/+5
2025-03-13AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)Matt Arsenault1-1/+1
2025-02-22PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)Matt Arsenault1-11/+11
2025-02-04DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)Matt Arsenault1-46/+13
2025-01-23[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)Lucas Ramirez1-11/+11
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-177/+177
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-177/+177
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-177/+177
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-204/+204
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-204/+204
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-204/+204
2024-05-23[llvm][ScheduleDAG] SUnit::biasCriticalPath() does not find the critical path...csstormq1-107/+109
2024-05-22Revert "[AMDGPU] Update test results to fix build (#92982)"Nikita Popov1-109/+107
2024-05-22[AMDGPU] Update test results to fix build (#92982)AtariDreams1-107/+109
2024-05-09[AMDGPU] Remove duplicate -mtriple options in tests (#91576)Jay Foad1-1/+1
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-1/+1
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin1-32/+27
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-11/+11
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-11/+11
2023-09-15[AMDGPU] Remove repeated -mtriple options from RUN lines (#66486)Jay Foad1-2/+2
2023-09-11[test] Change llc -march= to -mtriple=Fangrui Song1-2/+2
2023-04-10[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALUskc71-4/+4
2023-03-12Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5...Chen Zheng1-25/+17
2023-02-13Revert "[DAGCombiner] handle more store value forwarding"Arthur Eubanks1-17/+25
2023-02-01[DAGCombiner] handle more store value forwardingChen Zheng1-25/+17
2023-01-23AMDGPU: Clean up LDS-related occupancy calculationsNicolai Hähnle1-11/+11
2022-11-29AMDGPU: Convert some bit operation tests to opaque pointersMatt Arsenault1-111/+111
2022-07-14[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with ...Craig Topper1-11/+8
2022-07-14[AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.Alexander Timofeev1-3/+3
2022-05-18[AMDGPU] Aggressively fold immediates in SIShrinkInstructionsJay Foad1-3/+2
2022-01-26[LSV] Vectorize loads of vectors by turning it into a larger vectorBenjamin Kramer1-95/+80
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-465/+453
2021-11-24[AMDGPU] Only select VOP3 forms of VOP2 instructionsJay Foad1-7/+7
2021-11-24[AMDGPU] Check for unneeded shift mask in shift PatFrags.Abinav Puthan Purayil1-23/+14
2021-09-14RegAllocGreedy: Account for reserved registers in num regs heuristicMatt Arsenault1-16/+16
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash1-5/+5
2021-06-30[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constantsStanislav Mekhanoshin1-14/+10
2021-05-07[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shiftsSimon Pilgrim1-260/+224
2021-05-06[AMDGPU] Regenerate shift tests. NFCI.Simon Pilgrim1-572/+1144
2021-01-09[AMDGPU] Add volatile support to SIMemoryLegalizerTony1-3/+5
2021-01-07[NFC] Removed unused prefixes in CodeGen/AMDGPUMircea Trofin1-3/+3
2020-09-23Revert "[AMDGPU] Insert waitcnt after returning from call"Sebastian Neubauer1-0/+2
2020-09-23[AMDGPU] Insert waitcnt after returning from callSebastian Neubauer1-2/+0
2020-07-17[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristicsJay Foad1-28/+28
2020-05-01[AMDGPU] Remove unnecessary s_waitcnt between VMEM loadsJay Foad1-1/+1
2020-02-28[AMDGPU] Remove dubious logic in bidirectional list schedulerJay Foad1-45/+45
2020-02-10AMDGPU: Move R600 test compatability hackMatt Arsenault1-6/+6
2020-02-03[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions ...Jay Foad1-5/+5
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