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path: root/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
AgeCommit message (Expand)AuthorFilesLines
14 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-4/+4
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song1-21/+19
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song1-24/+24
2025-05-16[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)Pierre van Houtryve1-29/+15
2025-05-05[AMDGPU] SIPeepholeSDWA: Handle V_CNDMASK_B32_e64 (#137930)Frederik Harwath1-10/+8
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t1-8/+10
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber1-10/+8
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t1-8/+10
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault1-10/+8
2025-03-17[AMDGPU] Add identity_combines to RegBankCombiner (#131305)Pierre van Houtryve1-5/+5
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-125/+125
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-125/+125
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-125/+125
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve1-11/+17
2024-07-23[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)Christudasan Devadasan1-63/+63
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-83/+83
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-83/+83
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-83/+83
2024-05-17[SelectionDAG] Widen cttz to cttz_zero_undef (#92514)Jay Foad1-1/+0
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-4/+4
2023-12-25[LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (#75158)Acim Maravic1-28/+25
2023-12-18[DAG] Fold (vt trunc (extload (vt x))) -> (vt load x) (#75229)Simon Pilgrim1-8/+4
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-10/+10
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-10/+10
2023-09-19[CodeGen] Renumber slot indexes before register allocation (#66334)Jay Foad1-10/+10
2023-02-10[AMDGPU] Run unmerge combines post regbankselectPierre van Houtryve1-5/+5
2022-11-29AMDGPU: Convert some bit operation tests to opaque pointersMatt Arsenault1-49/+49
2022-11-16[AMDGPU][GISel] Smaller code for scalar 32 to 64-bit extensionsJay Foad1-4/+4
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson1-191/+192
2022-05-14[AMDGPU] Fix typo in cttz_zero_undef(x) -> cttz(x) fold testSimon Pilgrim1-52/+49
2021-12-20AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splittingMatt Arsenault1-47/+36
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-266/+269
2021-09-16[GlobalISel] Add a combine for and(load , mask) -> zextloadKonstantin Schwarz1-28/+8
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash1-1/+1
2021-08-06[GlobalISel] Improve widening of cttz/cttz_zero_undefJay Foad1-4/+2
2021-08-06[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttzJay Foad1-7/+5
2021-08-06[AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR ctlz_zero_undef/ct...Jay Foad1-6/+5
2021-08-05[AMDGPU][SDag] Better lowering for 32-bit ctlz/cttzJay Foad1-15/+10
2021-08-05[AMDGPU][SDag] Better lowering for 64-bit ctlz/cttzJay Foad1-15/+10
2021-08-05[AMDGPU] Add globalisel checks for ctlz_zero_undef/cttz_zero_undefJay Foad1-0/+335
2021-08-05[AMDGPU] Generate checks for ctlz_zero_undef/cttz_zero_undefJay Foad1-119/+1184
2020-07-30[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logichsmahesha1-3/+3
2020-07-17[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristicsJay Foad1-2/+2
2020-07-14[AMDGPU] Fix typos in performCtlz_CttzCombine()Jay Foad1-4/+4
2020-06-25[AMDGPU] Select s_cselectPiotr Sobczak1-2/+2
2020-06-19Revert "[AMDGPU] Select s_cselect"Piotr Sobczak1-2/+2
2020-06-19[AMDGPU] Select s_cselectPiotr Sobczak1-2/+2
2020-02-10AMDGPU: Move R600 test compatability hackMatt Arsenault1-4/+4
2020-02-07[LegalizeDAG][X86][AMDGPU] Use ANY_EXTEND instead of ZERO_EXTEND when promoti...Craig Topper1-3/+3
2020-02-03[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions ...Jay Foad1-5/+11
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