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path: root/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
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12 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-4/+4
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song1-21/+19
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song1-23/+23
2025-05-16[AMDGPU] Do not promote uniform i16 operations to i32 in CGP (#140208)Pierre van Houtryve1-9/+7
2025-05-05[AMDGPU] SIPeepholeSDWA: Handle V_CNDMASK_B32_e64 (#137930)Frederik Harwath1-7/+7
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t1-7/+10
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber1-10/+7
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t1-7/+10
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault1-10/+7
2025-03-17[AMDGPU] Add identity_combines to RegBankCombiner (#131305)Pierre van Houtryve1-9/+9
2025-03-13AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)Matt Arsenault1-1/+1
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-174/+174
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-174/+174
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-174/+174
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve1-7/+12
2024-07-25[GlobalIsel] Push cast through select. (#100539)Thorsten Schütt1-4/+5
2024-07-23[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)Christudasan Devadasan1-79/+79
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault1-136/+136
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung1-136/+136
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault1-136/+136
2024-07-08[LegalizeDAG] Optimize CodeGen for `ISD::CTLZ_ZERO_UNDEF` (#83039)Manish Kausik H1-72/+49
2024-05-20[AMDGPU] Fix error in #88512. (#92770)Leon Clark1-28/+48
2024-05-19[AMDGPU] Use LSH for lowering ctlz_zero_undef.i8/i16 (#88512)Leon Clark1-138/+94
2024-05-08AMDGPU: Add some more ctlz_zero_undef testsMatt Arsenault1-0/+473
2024-02-29[AMDGPU] Fix OpenCL conformance test failures for ctlz. (#83170)Leon Clark1-38/+39
2024-01-19[AMDGPU] Remove unnecessary add instructions in ctlz.i8 (#77615)Leon Clark1-42/+39
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-4/+4
2023-12-25[LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (#75158)Acim Maravic1-16/+787
2022-11-29AMDGPU: Convert some bit operation tests to opaque pointersMatt Arsenault1-65/+65
2022-11-16[AMDGPU][GISel] Smaller code for scalar 32 to 64-bit extensionsJay Foad1-1/+1
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson1-189/+172
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-175/+175
2021-09-16[GlobalISel] Add a combine for and(load , mask) -> zextloadKonstantin Schwarz1-2/+1
2021-08-06[AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR ctlz_zero_undef/ct...Jay Foad1-10/+8
2021-08-05[AMDGPU][SDag] Better lowering for 64-bit ctlz/cttzJay Foad1-37/+25
2021-08-05[AMDGPU] Add globalisel checks for ctlz_zero_undef/cttz_zero_undefJay Foad1-0/+261
2021-08-05[AMDGPU] Generate checks for ctlz_zero_undef/cttz_zero_undefJay Foad1-112/+981
2020-08-09Fix 64-bit copy to SCCPiotr Sobczak1-3/+7
2020-06-25[AMDGPU] Select s_cselectPiotr Sobczak1-4/+3
2020-06-24Revert "[AMDGPU] Enable compare operations to be selected by divergence"Matt Arsenault1-1/+1
2020-06-24[AMDGPU] Enable compare operations to be selected by divergencealex-t1-1/+1
2020-06-19Revert "[AMDGPU] Select s_cselect"Piotr Sobczak1-3/+4
2020-06-19[AMDGPU] Select s_cselectPiotr Sobczak1-4/+3
2020-02-10AMDGPU: Move R600 test compatability hackMatt Arsenault1-15/+15
2018-09-11[AMDGPU] Preliminary patch for divergence driven instruction selection. Immed...Alexander Timofeev1-1/+1
2018-06-26AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault1-2/+2
2017-11-20[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky1-1/+1
2017-07-06AMDGPU: Add macro fusion schedule DAG mutationMatt Arsenault1-2/+2
2017-07-04[AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev1-26/+48
2017-07-04Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi1-48/+26
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