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path: root/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
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11 days[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian1-1/+1
2025-04-24AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)Matt Arsenault1-2/+0
2025-03-13AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)Matt Arsenault1-2/+2
2025-03-12AMDGPU: Replace undef with poison in tests using insertvalue (#130895)Matt Arsenault1-1/+1
2025-03-04DAG: Use phi to create vregs instead of the constant input (#129464)Matt Arsenault1-2/+2
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov1-12/+12
2025-01-24[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)Aaditya1-4/+4
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian1-28/+32
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian1-32/+28
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian1-28/+32
2024-03-06[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)Emma Pilkington1-1/+1
2024-02-09Revert "[AMDGPU] Compiler should synthesize private buffer resource descripto...Jan Patrick Lehr1-6/+4
2024-02-08[AMDGPU] Compiler should synthesize private buffer resource descriptor from f...alex-t1-4/+6
2023-12-12[AMDGPU][NFC] Test autogenerated llc tests for COV5 (#74339)Saiyedul Islam1-32/+31
2023-10-27[AMDGPU] Try to fix the block prologs broken by RA inserted instructions (#69...Christudasan Devadasan1-1/+1
2023-09-12Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#...Saiyedul Islam1-28/+32
2023-09-12[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)Saiyedul Islam1-32/+28
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault1-16/+8
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka1-8/+16
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-16/+8
2023-05-05AMDGPU/SDAG: Improve {extract,insert}_subvector lowering for 16-bit vectorsNicolai Hähnle1-2/+0
2023-03-28[AMDGPU] Break-up large PHIs for DAGISelpvanhout1-8/+6
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan1-4/+0
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov1-2/+2
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-0/+4
2022-12-17[AMDGPU][SIFrameLowering] Use the right frame register in CSR spillsChristudasan Devadasan1-40/+48
2022-12-17[AMDGPU] Separate out SGPR spills to VGPR lanes during PEIChristudasan Devadasan1-8/+16
2022-11-29Revert "enable code-object-version=5"Ron Lieberman1-28/+32
2022-11-29enable code-object-version=5Ron Lieberman1-32/+28
2022-09-28AMDGPU: Make various vector undefs legalMatt Arsenault1-2/+2
2022-03-09[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...Venkata Ramanaiah Nalamothu1-20/+20
2021-12-22Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to cal...Ron Lieberman1-20/+20
2021-12-22[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...RamNalamothu1-20/+20
2021-12-04AMDGPU: Enable fixed function ABI by defaultMatt Arsenault1-42/+58
2021-11-20[AMDGPU] Do not generate ELF symbols for the local branch target labelsRamNalamothu1-8/+8
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash1-8/+8
2021-09-09AMDGPU: Invert ABI attribute handlingMatt Arsenault1-8/+8
2021-09-01[AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstrStanislav Mekhanoshin1-2/+2
2021-09-01[AMDGPU] Introduce optimizeCompareInstrStanislav Mekhanoshin1-2/+0
2021-09-01 [AMDGPU] enable scalar compare in truncate selectionalex-t1-2/+4
2021-06-07[AMDGPU] Use s_add_i32 for address additionsSebastian Neubauer1-8/+8
2021-04-13[AMDGPU] Set implicit arg attributes for indirect callsmadhur134901-138/+126
2021-02-19Make fixed-abi default for AMD HSA OSmadhur134901-126/+138
2020-10-29[AMDGPU] Use pseudo instructions for readlane/writelaneJay Foad1-1/+1
2020-09-23Revert "[AMDGPU] Insert waitcnt after returning from call"Sebastian Neubauer1-6/+4
2020-09-23[AMDGPU] Insert waitcnt after returning from callSebastian Neubauer1-4/+6
2020-09-02[AMDGPU] Fix offset for REL32_HI relocsJay Foad1-6/+6
2020-05-05[AMDGPU] Introduce more scratch registers in the ABI.Christudasan Devadasan1-32/+32
2020-04-06[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Konstantin Pyzhov1-16/+16
2020-04-06Revert e1730cfeb3588f20dcf4a96b181ad52761666e52Konstantin Pyzhov1-16/+16
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