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path: root/llvm/test/Analysis/CostModel/RISCV
AgeCommit message (Expand)AuthorFilesLines
9 days[RISCV] Fix bug in [l](lrint|lround) vector-cost (#151298)Ramkumar Ramachandra1-12/+12
10 daysRevert "[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal withou...Luke Lau1-4/+4
10 days[CostModel/RISCV] Fix costs of vector [l](lrint|lround) (#146058)Ramkumar Ramachandra1-237/+389
11 days[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmi...Luke Lau1-4/+4
12 days[RISCV] Add FP cost model tests for no zfhmin/zfbfmin. NFCLuke Lau1-445/+1270
12 days[RISCV] Modernize FP cost model tests. NFCLuke Lau1-1417/+1426
2025-07-24[TTI] Share value and type based llvm.vector.reverse cost (#150415)Luke Lau2-192/+95
2025-07-24[RISCV] Add type based RUN line for vector intrinsic cost model tests. NFCLuke Lau1-44/+91
2025-07-23[RISCV][TTI] Implement vector costs for `llvm.fpto{u|s}i.sat()`. (#143655)Elvis Wang1-304/+304
2025-07-11[TTI] Fix value-based BasicTTIImpl vp.{gather,scatter} costing (#148020)Luke Lau1-0/+116
2025-07-10[TTI] Handle experimental.vp.reverse in BasicTTIImpl (#147868)Luke Lau1-0/+228
2025-07-10[TTI] Don't drop VP intrinsic args when delegating to non-vp equivalent (#147...Luke Lau1-0/+106
2025-07-10[RISCV] Unify non-vp and vp rounding intrinsic costing (#147872)Luke Lau1-165/+165
2025-07-10[TTI] Check type legalization of both src and result for fpto{u|s}i.sat. (#14...Elvis Wang1-0/+583
2025-07-08[RISCV] Remove intrinsic declares from costmodel tests. NFCLuke Lau24-1916/+0
2025-07-07[BasicTTIImpl] Add cost entries for ldexp, [l]lround (#146373)Ramkumar Ramachandra1-25/+25
2025-06-28[CostModel/RISCV] Add tests for ldexp, [l]lround (#146108)Ramkumar Ramachandra2-0/+303
2025-06-26[CostModel] getInstructionCost - match SK_InsertSubvector shuffle patterns be...Simon Pilgrim3-76/+76
2025-06-16[RISCV][TTI] Refine reverse shuffle costing for high LMUL (#144155)Philip Reames2-60/+60
2025-06-16[TargetLowering][RISCV] Allow scalable non-simple EVTs to be split even if th...Craig Topper3-4508/+2260
2025-06-12[RISCV][CostModel] Add additional high LMUL reverse testsPhilip Reames2-0/+15
2025-05-30[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available (#14...Philip Reames2-0/+594
2025-04-28[CostModel] Remove some negative costs. (#135533)David Green1-6/+6
2025-04-22[RISCV][TTI] Use processShuffleMask for shuffle legalization estimate (#136191)Philip Reames2-282/+157
2025-04-21[RISCV] Handle scalarized reductions in getArithmeticReductionCostLuke Lau1-32/+135
2025-04-17[RISCV] Add a couple of cost model tests for shuffles requiring legalizationPhilip Reames1-0/+30
2025-03-29[RISCV][TTI] Adjust VLS shuffle costing to account for sub-mask reuse (#129793)Philip Reames1-4/+4
2025-03-07[CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (#12...Benjamin Maxwell5-7/+7
2025-03-05[RISCV] Fix a typo in fixed_m2_in_m4_tail test [nfc]Philip Reames1-12/+12
2025-03-04[RISCV][CostModel] Add additional deinterleave tests with EMUL>1Philip Reames1-0/+30
2025-03-04[RISCV] Fix a typo in fixed_m1_in_m2_tail test [nfc]Philip Reames1-6/+6
2025-03-03[RISCV] Tune flag for fast vrgather.vv (#124664)Petr Penzin1-0/+51
2025-02-28Reapply "[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)"Philip Reames3-39/+39
2025-02-27Revert "[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)"Philip Reames3-39/+39
2025-02-27[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)Philip Reames3-39/+39
2025-02-21[TTI][AArch64] Detect OperandInfo from scalable splats. (#122469)David Green1-4/+4
2025-02-10[RISCV] Add cost model for fma (#126076)Mikhail R. Gadelha1-47/+31
2025-02-05[RISCV] Added cost model for fmuladd (#125683)Mikhail R. Gadelha1-41/+28
2025-02-05[RISCV][TTI] Fix test fails for #124221 NFC. (#125792)Elvis Wang1-17/+0
2025-02-05[RISCV][TTI] Implement instruction cost for vp.splice. (#124221)Elvis Wang1-0/+52
2025-02-04[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsic...Sergey Kachkov2-4/+181
2025-02-01[CostModel][RISCV] vp-intrinsics.ll - add common check prefix for ARGBASED + ...Simon Pilgrim1-768/+31
2025-02-01[TTI] getTypeBasedIntrinsicInstrCost - add basic handling for strided load/st...Simon Pilgrim1-44/+44
2025-01-31Revert 48a66e9b2a9a5083f26c95b14b09c9c897780f59 "[TTI] getTypeBasedIntrinsicI...Simon Pilgrim1-44/+44
2025-01-31[TTI] getTypeBasedIntrinsicInstrCost - add basic handling for strided load/st...Simon Pilgrim1-44/+44
2025-01-29[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register ...Alexey Bataev3-100/+80
2025-01-24[CostModel] getTypeBasedIntrinsicInstrCost - add default cost approximations ...Simon Pilgrim1-2/+2
2025-01-10[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 (#118608)LiqinWeng2-152/+186
2025-01-10[RISCV] Fix the cost of `llvm.vector.reduce.and` (#119160)Shao-Ce SUN4-20/+259
2025-01-03[RISCV][NFC] precommit test for fcmp with f16ShihPo Hung2-253/+678
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