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path: root/llvm/lib/Target/VE/VEISelLowering.h
AgeCommit message (Expand)AuthorFilesLines
2025-01-20[Mips] Fix compiler crash when returning fp128 after calling a functi… (#11...yingopq1-1/+2
2023-08-30[VE] Remove CodeGen deps from MCTargetDesc, NFCReid Kleckner1-0/+90
2023-04-02[Targets] Rename Flag->Glue. NFCCraig Topper1-1/+1
2023-01-09[VE] Use generic MEMBARRIER SDAG node [nfc]Philip Reames1-1/+0
2022-11-17[AMDGPU] Allow finer grain control of an unaligned access speedStanislav Mekhanoshin1-1/+1
2022-10-20[VE] Change the way to lower selectccKazushi (Jam) Marukawa1-0/+5
2022-10-15[VE] Change the way to lower selectKazushi (Jam) Marukawa1-0/+3
2022-08-24[X86] Promote i8/i16 CTTZ (BSF) instructions and remove speculation branchSimon Pilgrim1-1/+1
2022-03-14[VE] v256.32|64 gather|scatter isel and testsSimon Moll1-1/+2
2022-03-07[VE] Split v512.32 load store into interleaved v256.32 opsSimon Moll1-0/+2
2022-03-02[VE] (masked) load|store v256.32|64 iselSimon Moll1-0/+2
2022-02-22[VE] Split unsupported v512.32 opsSimon Moll1-0/+1
2022-02-21[VE] v512i1 mask arithmetic iselSimon Moll1-2/+9
2022-02-02[VE] LEGALAVL and staged VVP legalizationSimon Moll1-0/+12
2022-01-26[VE] Packed 32/64bit broadcast isel and testsSimon Moll1-0/+2
2022-01-07[NFC] Fix endif comments to match with include guardQiu Chaofan1-1/+1
2021-07-19[VE] Set getExtendForAtomicOps to ISD::ANY_EXTENDKazushi (Jam) Marukawa1-0/+3
2021-06-08[VE][NFC] IRBuilder<> -> IRBuilderBaseSimon Moll1-2/+2
2021-02-04[VE] Fix allowsMisalignedMemoryAccesses after D96097Fangrui Song1-1/+1
2021-01-08[VE] Extract & insert vector element iselSimon Moll1-0/+2
2021-01-05[VE] Support SJLJ exception related instructionsKazushi (Jam) Marukawa1-13/+42
2021-01-05[VE] Support llvm.eh.sjlj.lsdaKazushi (Jam) Marukawa1-0/+1
2020-12-15[VE][NFC] Sort VEISD operationsKazushi (Jam) Marukawa1-14/+11
2020-12-15[VE] Support atomic exchange instructionsKazushi (Jam) Marukawa1-2/+12
2020-11-23[VE] VE Vector Predicated SDNode, vector add isel and testsSimon Moll1-0/+8
2020-11-20[VE] Change threshold for jump table generationKazushi (Jam) Marukawa1-0/+3
2020-11-19[VE] VEC_BROADCAST, lowering and iselSimon Moll1-0/+4
2020-11-17[VE] Implement JumpTableKazushi (Jam) Marukawa1-0/+10
2020-11-10[VE] Support inline assembly with vector regsitersKazushi (Jam) Marukawa1-0/+1
2020-11-10[VE] Support inline assemblyKazushi (Jam) Marukawa1-0/+8
2020-11-04[VE] Add +vpu attributeSimon Moll1-1/+1
2020-10-30[VE][NFC] Split up lowering initSimon Moll1-0/+4
2020-10-26[VE] Support atomic loadKazushi (Jam) Marukawa1-0/+10
2020-10-26[VE] Support atomic fenceKazushi (Jam) Marukawa1-0/+3
2020-08-18[VE] Modify ISelLoweirng following clang-tidyKazushi (Jam) Marukawa1-7/+7
2020-08-17[VE] Support f128Kazushi (Jam) Marukawa1-0/+4
2020-08-11[VE] Update bit operationsKazushi (Jam) Marukawa1-3/+13
2020-08-07[VE] Optimize trunc related instructionsKazushi (Jam) Marukawa1-0/+6
2020-06-09[VE] Support lowering to NND instructionKazushi (Jam) Marukawa1-0/+2
2020-05-27[VE] Dynamic stack allocationKazushi (Jam) Marukawa1-2/+5
2020-05-04[VE][NFC] formatting VEISD enumSimon Moll1-2/+2
2020-02-18[VE] TLS codegenKazushi (Jam) Marukawa1-0/+4
2020-02-14[VE] Support for PIC (global data and calls)Kazushi (Jam) Marukawa1-1/+3
2020-02-03[VE] vaarg functions callers and calleesKazushi (Jam) Marukawa1-0/+2
2020-01-29[VE] (conditional) branch modification & isel patternsKazushi (Jam) Marukawa1-0/+1
2020-01-29[VE] udiv/sdiv/urem/srem/mul isel patternsKazushi (Jam) Marukawa1-0/+3
2020-01-28[VE] call isel with stack passingKazushi (Jam) Marukawa1-0/+4
2020-01-28[VE] enable unaligned load/store iselKazushi (Jam) Marukawa1-0/+5
2020-01-24[VE] global variable isel patternsKazushi (Jam) Marukawa1-0/+15
2020-01-22[VE] i<N> and fp32/64 arguments, return values and constantsKazushi (Jam) Marukawa1-0/+6
generated by cgit v1.1 at 2025-08-06 09:51:50 +0000