aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
AgeCommit message (Expand)AuthorFilesLines
11 days[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolic...Harrison Hao1-3/+3
2025-05-24[RISCV] Remove unused includes (NFC) (#141378)Kazu Hirata1-2/+0
2025-04-15[RISCV] Fix xmipscmov extension name (#135647)Djordje Todorovic1-1/+1
2025-03-07[RISCV] Generate MIPS load/store pair instructions (#124717)Djordje Todorovic1-7/+11
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+13
2024-12-19[RISCV] Add software pipeliner support (#117546)Pengcheng Wang1-0/+4
2024-12-16[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (...Sergei Barannikov1-1/+10
2024-12-16[RISCV] Add tune info for postra scheduling direction (#115864)Pengcheng Wang1-1/+15
2024-11-28[RISCV] Add TuneDisableLatencySchedHeuristicPengcheng Wang1-0/+4
2024-11-26[RISCV] Remove getPostRAMutations (#117527)Pengcheng Wang1-5/+0
2024-11-15[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)Pengcheng Wang1-0/+13
2024-08-08[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)Craig Topper1-1/+2
2024-07-10[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC...Craig Topper1-3/+2
2024-07-10[RISCV][GISEL] Do not initialize GlobalISel objects unless needed (#98233)Michael Maitland1-9/+12
2024-06-14[CodeGen] Remove target SubRegLiveness flags (#95437)David Green1-8/+1
2024-01-25[RISCV] Use TableGen-based macro fusion (#72224)Wang Pengcheng1-2/+6
2023-11-23[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)Wang Pengcheng1-0/+10
2023-09-26[RISCV] Add searchable table for tune information (#66193)Wang Pengcheng1-0/+12
2023-09-01[RISCV] Remove XLen field from RISCVSubtarget [nfc]Philip Reames1-3/+0
2023-08-31[RISCV] Kill off redundant field XLenVT [nfc]Philip Reames1-3/+1
2023-08-10[RISCV] Enable alias analysis by defaultYunze Zhu1-0/+7
2023-06-02[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizesNitin John Raj1-1/+1
2023-04-12[CodeGen][RISCV] Change Shadow Call Stack Register to X3Paul Kirth1-3/+0
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper1-2/+2
2023-03-08[RISCV] Enable subregister liveness by defaultPiyou Chen1-1/+1
2023-02-15Use llvm::has_single_bit<uint32_t> (NFC)Kazu Hirata1-1/+2
2023-02-05[RISCV] Default to -ffixed-x18 for FuchsiaRoland McGrath1-0/+3
2023-02-05[RISCV] clang-format #include. NFCFangrui Song1-3/+3
2023-01-28[RISCV] Use llvm::bit_floor and std::clamp (NFC)Kazu Hirata1-2/+1
2022-12-20[RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine.Craig Topper1-45/+9
2022-11-15[RISCV] Move GlobalISEL specific files to sub-directory [nfc]Philip Reames1-3/+3
2022-08-26[RISCV] Enable fixed length vectors and loop vectorization with samePhilip Reames1-1/+1
2022-08-25[RISCV][M68k] Replace fixed size BitVector with std::bitset.Craig Topper1-2/+2
2022-07-14[RISCV] Disable subregister liveness by defaultFraser Cormack1-5/+3
2022-06-23[RISCV] Add macrofusion infrastructure and one example usage.Craig Topper1-0/+6
2022-06-20Recommit "[RISCV] Enable subregister liveness tracking for RVV."Craig Topper1-2/+5
2022-05-13Revert "[RISCV] Enable subregister liveness tracking for RVV."Craig Topper1-5/+2
2022-05-11[RISCV] Enable subregister liveness tracking for RVV.Craig Topper1-0/+11
2022-05-04[RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use...Craig Topper1-7/+13
2022-04-11[RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option.Craig Topper1-16/+0
2022-03-09[RISCV] Support 'generic' as a valid CPU name.Craig Topper1-4/+1
2022-01-26[RISCV] Fix support of vlen = 64.jacquesguan1-11/+13
2022-01-20[RISCV] Factor Zve32 support into RISCVSubtarget::getMaxELENForFixedLengthVec...Craig Topper1-1/+2
2022-01-14[RISCV] Add the zvl extension according to the v1.0 speceopXD1-2/+18
2021-12-31[RISCV] Use constant pool for large integerswangpc1-0/+25
2021-10-27[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCICraig Topper1-8/+9
2021-10-08Move TargetRegistry.(h|cpp) from Support to MCReid Kleckner1-1/+1
2021-08-27[RISCV] Add -riscv-v-fixed-length-vector-elen-max to limit the ELEN used for ...Craig Topper1-1/+17
2021-07-17[RISCV] Make VLEN no greater than 65536jacquesguan1-8/+10
2021-04-23[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.Craig Topper1-12/+0
generated by cgit v1.1 at 2025-08-02 12:56:13 +0000