| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-07-09 | [RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructio... | Min-Yih Hsu | 1 | -0/+35 |
| 2025-07-09 | [RISCV] Add scheduling info for XSfvfnrclipxfqf instructions (#147586) | Min-Yih Hsu | 1 | -0/+27 |
| 2025-06-25 | [RISCV] Fix incorrect chapter number in comment in RISCVSchedSiFive7.td. NFC. | Jim Lin | 1 | -6/+6 |
| 2025-06-23 | [RISCV] Add SiFive X390 scheduling model (#143938) | Min-Yih Hsu | 1 | -162/+233 |
| 2025-06-23 | [RISCV] Factor out common SiFive7 scheduling model into an abstraction layer ... | Min-Yih Hsu | 1 | -1003/+1070 |
| 2025-06-10 | [RISCV][NFC] Factor out VLEN in the SiFive7 scheduling model (#143629) | Min-Yih Hsu | 1 | -34/+30 |
| 2025-05-15 | [RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495) | Iris Shi | 1 | -0/+1 |
| 2025-02-07 | [RISCV] Fix typos discovered by codespell (NFC) (#126191) | Sudharsan Veeravalli | 1 | -2/+2 |
| 2025-01-29 | [RISCV][SIFIVE] Fix latencies for vector integer arithmetic long latency (#12... | Michael Maitland | 1 | -7/+9 |
| 2024-11-01 | [llvm][NFC] Fix typos: replace “avaliable” with “available” across va... | Wang Qiang | 1 | -1/+1 |
| 2024-10-28 | [RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009) | Min-Yih Hsu | 1 | -0/+3 |
| 2024-09-05 | [RISCV][SiFive7] Change `Latency` of VCIX to the default (#106497) | Michal Terepeta | 1 | -4/+7 |
| 2024-09-01 | [RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (... | Craig Topper | 1 | -4/+0 |
| 2024-07-30 | [RISCV] Rename merge operand -> passthru. NFC (#100330) | Luke Lau | 1 | -3/+3 |
| 2024-05-24 | [RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781) | Michael Maitland | 1 | -1/+0 |
| 2024-05-23 | [RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768) | Michael Maitland | 1 | -0/+3 |
| 2024-05-20 | [RISCV] Split and rename WriteVISlideX into WriteVSlideUpX and WriteVSlideDow... | Min-Yih Hsu | 1 | -4/+5 |
| 2024-05-03 | [RISCV] Add Sched classes for vector crypto instructions (#90068) | Michael Maitland | 1 | -0/+1 |
| 2024-04-16 | [RISCV] Add scheduling information for SiFive VCIX (#86093) | Michal Terepeta | 1 | -0/+48 |
| 2024-04-15 | [RISCV] Split PseudoVFMIN, PseudoVFMAX PseudoVFSGNJ, PseudoVFSGNJN, and Pseud... | Michael Maitland | 1 | -8/+10 |
| 2024-04-15 | [RISCV] Split narrowing convert to FP pseudos by SEW | Michael Maitland | 1 | -7/+9 |
| 2024-04-15 | [RISCV] Split Widening convert to FP pseudos by SEW | Michael Maitland | 1 | -12/+10 |
| 2024-04-15 | [RISCV] Split single width convert to FP pseudos by SEW | Michael Maitland | 1 | -2/+2 |
| 2024-04-12 | [RISCV] Split PseudoVFRSQRT7 and PseudoVFREC7 by SEW | Michael Maitland | 1 | -2/+2 |
| 2024-04-12 | [RISCV] Split widening floating point fused multiple-add pseudo instructions ... | Michael Maitland | 1 | -4/+4 |
| 2024-04-12 | [RISCV] Split single width floating point fused multiple-add pseudo instructi... | Michael Maitland | 1 | -4/+4 |
| 2024-04-12 | [RISCV] Split PseudoVFMUL by SEW | Michael Maitland | 1 | -4/+4 |
| 2024-04-12 | [RISCV] Split PseudoVFWADD, PseudoVFWSUB, and PseudoVFWMUL by SEW | Michael Maitland | 1 | -8/+16 |
| 2024-04-12 | [RISCV] Split PseudoVFADD, PseudoVFSUB, and PseudoVFRSUB by SEW | Michael Maitland | 1 | -4/+12 |
| 2024-04-01 | [RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454) | Michael Maitland | 1 | -1/+1 |
| 2024-03-14 | [RISCV] Model integer min max instructions from Zbb execute in late-B ALU | Michael Maitland | 1 | -1/+2 |
| 2024-03-14 | [RISCV] Add sched classes for Zbb integer min max instructions | Michael Maitland | 1 | -1/+4 |
| 2024-03-11 | [RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s ... | Philip Reames | 1 | -10/+10 |
| 2024-03-07 | [RISCV] Split div vs rem scheduling information [nfc] (#84385) | Philip Reames | 1 | -0/+13 |
| 2024-02-29 | [RISCV] Enable PostRAScheduler for SiFive7 (#83166) | Michael Maitland | 1 | -0/+1 |
| 2024-02-06 | [RISCV] Adjust a few vector scheduler class names. NFC (#80795) | Craig Topper | 1 | -3/+3 |
| 2024-01-31 | [RISCV][MC] Add MC layer support for the experimental zabha extension (#80005) | Yingwei Zheng | 1 | -0/+1 |
| 2023-12-19 | [RISCV][MISched] Set EnableIntervals to true for SiFive7 (#75681) | Michael Maitland | 1 | -0/+1 |
| 2023-12-04 | [RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969) | Michael Maitland | 1 | -236/+242 |
| 2023-12-04 | [RISCV] Rework IDiv and FDiv pipes on SiFive7 (#73970) | Michael Maitland | 1 | -2/+2 |
| 2023-11-27 | [RISCV] Add Zbs Write classes to SiFive7AnyToGPRBypass. (#72560) | Craig Topper | 1 | -0/+2 |
| 2023-10-30 | [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266) | Michael Maitland | 1 | -7/+27 |
| 2023-10-26 | [RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241) | Yingwei Zheng | 1 | -0/+3 |
| 2023-09-05 | [RISCV] Fix SiFive7 formula for Reductions and ordered Reductions (#65385) | Michael Maitland | 1 | -3/+3 |
| 2023-08-28 | [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiF... | Craig Topper | 1 | -5/+6 |
| 2023-08-24 | [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics | Michael Maitland | 1 | -65/+65 |
| 2023-08-24 | Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics" | Michael Maitland | 1 | -65/+65 |
| 2023-08-24 | [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics | Michael Maitland | 1 | -65/+65 |
| 2023-08-24 | Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics" | Michael Maitland | 1 | -65/+65 |
| 2023-08-24 | [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics | Michael Maitland | 1 | -65/+65 |
