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path: root/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
3 days[RISCV] Fix a warningKazu Hirata1-1/+0
4 days[RISCV] Handled the uimm9 offset while FrameIndex folding. (#149303)UmeshKalappa1-0/+5
4 days[RISCV] Support PreserveMost calling convention (#148214)Pengcheng Wang1-1/+10
2025-06-23[RISCV][NFC] Remove hasStdExtCOrZca (#145139)Sam Elliott1-2/+1
2025-06-18[RISCV] Save vector registers in interrupt handler. (#143808)Craig Topper1-0/+10
2025-05-16[RISCV] Use QC_E_ADDI while eliminating the frameindex (#139515)Sudharsan Veeravalli1-0/+24
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-0/+3
2025-05-09[RISCV] Remove X16-31 from interrupt callee saved register list for RVE+D. (#...Craig Topper1-1/+2
2025-03-28[RISCV] Refine location size for segment spill and fill (#133268)Philip Reames1-4/+8
2025-03-26[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)Philip Reames1-2/+9
2025-03-21[RISCV] Introduce RISCV::RVVBytesPerBlock to simplify code [nfc] (#132436)Philip Reames1-4/+4
2025-03-21[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)Kito Cheng1-12/+39
2025-03-13[RegAlloc] Scale the spill weight by target factor (#113675)Pengcheng Wang1-0/+5
2025-02-07[RISCV] Fix typos discovered by codespell (NFC) (#126191)Sudharsan Veeravalli1-1/+1
2025-02-04[RISCV] Implement getIPRACSRegs hook (#125586)Mikhail R. Gadelha1-0/+5
2025-01-27[RISCV] Add register allocation hints for lui/auipc+addi fusion. (#123860)Craig Topper1-0/+20
2024-12-06[RISCV][MRI] Account for fixed registers when determining callee saved regs (...Michael Maitland1-1/+1
2024-11-25[RISCV] Fix a warningKazu Hirata1-1/+0
2024-11-25[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)Philip Reames1-13/+17
2024-11-11[RISCV] Remove unused includes (NFC) (#115814)Kazu Hirata1-1/+0
2024-09-30[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)Brandon Wu1-0/+6
2024-09-26[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)Craig Topper1-7/+7
2024-09-24[RISCV] Use RVVBitsPerBlock in assignRVVStackObjectOffsets and adjustReg. NFC...Craig Topper1-3/+3
2024-09-03[RISCV] Rename `vcix_state` register to `sf_vcix_state`. NFC (#106995)Brandon Wu1-1/+1
2024-06-23[RISCV] Mark all registers marked isConstant as reserved (#96002)Francis Visoiu Mistrih1-3/+5
2024-05-13[RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve i...Craig Topper1-1/+2
2024-05-13[RISCV] Exclude vector callee saved registers from RISCVRegisterInfo::needsFr...Craig Topper1-2/+10
2024-05-13[RISCV] Don't exlude the frame pointer from the callee saved registers in RIS...Craig Topper1-2/+2
2024-05-13[RISCV] Don't add getFrameIndexInstrOffset in RISCVRegisterInfo::needsFrameBa...Craig Topper1-1/+0
2024-04-19[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)Craig Topper1-6/+6
2024-04-17[RISCV] Speed up RISCVRegisterInfo::needsFrameBaseReg when frame pointer isn'...Craig Topper1-10/+12
2024-04-10[RISCV] Address review comment from 88062Philip Reames1-2/+1
2024-04-09[RISCV] Use shNadd for scalable stack offsets (#88062)Philip Reames1-4/+15
2024-04-08[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (...Philip Reames1-0/+25
2024-04-08[RISCV] Eliminate getVLENFactoredAmount and expose muladd [nfc] (#87881)Philip Reames1-1/+10
2024-03-27[RISCV] RISCV vector calling convention (1/2) (#77560)Brandon Wu1-0/+15
2024-03-21[RISCV] Lower the alignment requirement for a GPR pair spill for Zdinx on RV3...Craig Topper1-0/+7
2024-03-20[RISCV] Convert an assertion to an if condition in getRegAllocationHints (#85...Craig Topper1-2/+5
2024-03-19[RISCV] Refactor code to reduce nesting and remove repeated calls to getOpcod...Craig Topper1-13/+12
2024-02-28[RISCV] Add a command line option to disable cost per use for compressed regi...Craig Topper1-1/+6
2024-02-20[RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc]Philip Reames1-4/+4
2024-02-13[RISCV] Register fixed stack slots for callee saved registers for -msave-rest...Craig Topper1-34/+0
2024-01-24[RISCV] Allow VCIX with SE to reorder (#77049)Brandon Wu1-0/+3
2024-01-23[RISCV] Add regalloc hints for Zcb instructions. (#78949)Craig Topper1-6/+34
2024-01-16[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)Wang Pengcheng1-2/+15
2024-01-14[RISCV] Combine repeated calls to MachineFunction::getSubtarget. NFCCraig Topper1-6/+6
2023-12-30[RISCV] Add MC layer support for Zicfiss. (#66043)Yeting Kuo1-0/+3
2023-12-05[RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)Craig Topper1-12/+28
2023-11-17[IR] Add GraalVM calling conventionsSacha Coppey1-1/+9
2023-10-24[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)Luke Lau1-0/+8
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