| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 8 days | [RISCV][ISel] Select `binvi` for pattern `icmp eq/ne X, pow2` (#110957) | Yingwei Zheng | 1 | -0/+8 |
| 9 days | [RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336) | Craig Topper | 1 | -0/+3 |
| 14 days | [RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446) | Craig Topper | 1 | -1/+4 |
| 2024-09-24 | [NFC] Fix typos in comments (#109765) | Piotr Fusik | 1 | -1/+1 |
| 2024-09-19 | [RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#1... | Craig Topper | 1 | -30/+0 |
| 2024-09-11 | [RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#1... | Craig Topper | 1 | -13/+4 |
| 2024-09-11 | [RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int... | Craig Topper | 1 | -1/+15 |
| 2024-09-06 | [RISCV] Move vmerge same mask peephole to RISCVVectorPeephole (#106108) | Luke Lau | 1 | -37/+5 |
| 2024-09-04 | [RISCV] Fix another RV32 Zdinx load/store addressing corner case. | Craig Topper | 1 | -1/+1 |
| 2024-08-31 | [llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995) | Brandon Wu | 1 | -146/+129 |
| 2024-08-30 | [RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517) | Luke Lau | 1 | -6/+5 |
| 2024-08-25 | [RISCV] Fix more boundary cases in immediate selection for Zdinx load/store o... | Craig Topper | 1 | -12/+44 |
| 2024-08-23 | Recommit "[RISCV] Add isel optimization for (and (sra y, c2), c1) to recover ... | Craig Topper | 1 | -2/+50 |
| 2024-08-23 | Revert "[RISCV] Add isel optimization for (and (sra y, c2), c1) to recover re... | Hans Wennborg | 1 | -50/+2 |
| 2024-08-20 | [RISCV] Add isel optimization for (and (sra y, c2), c1) to recover regression... | Craig Topper | 1 | -2/+50 |
| 2024-08-17 | [RISCV] Use getAllOnesConstant/getSignedConstant. | Craig Topper | 1 | -40/+47 |
| 2024-08-17 | [RISCV] Move vmv.v.v peephole from SelectionDAG to RISCVVectorPeephole (#100367) | Luke Lau | 1 | -70/+14 |
| 2024-08-16 | [RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802) | Wang Yaduo | 1 | -0/+9 |
| 2024-08-14 | [RISCV] Use if init statement to reduce scope of variable. NFC | Craig Topper | 1 | -7/+5 |
| 2024-08-08 | [RISCV] Add some Zfinx instructions to hasAllNBitUsers. | Craig Topper | 1 | -0/+6 |
| 2024-08-06 | [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in som... | Craig Topper | 1 | -1/+6 |
| 2024-08-05 | [RISCV] Improve variable scoping in custom isel for ISD::AND. | Craig Topper | 1 | -5/+6 |
| 2024-08-04 | [RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868) | Craig Topper | 1 | -0/+25 |
| 2024-08-05 | [RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123) | Luke Lau | 1 | -1/+3 |
| 2024-08-03 | [RISCV] Invert if conditions in the switch in RISCVDAGToDAGISel::hasAllNBitUs... | Craig Topper | 1 | -30/+30 |
| 2024-08-03 | [RISCV] Capitalize some variable names. NFC | Craig Topper | 1 | -4/+4 |
| 2024-07-31 | [RISCV] Fix vmerge.vvm/vmv.v.v getting folded into ops with mismatching EEW (... | Luke Lau | 1 | -0/+4 |
| 2024-07-30 | [RISCV] Rename merge operand -> passthru. NFC (#100330) | Luke Lau | 1 | -19/+19 |
| 2024-07-29 | [RISCV] Qualify all XCV predicates with !is64Bit. (#101074) | Craig Topper | 1 | -1/+1 |
| 2024-07-29 | [RISCV] Add isel special case for (and (srl X, c2), c1) -> (slli_uw (srli x, ... | Craig Topper | 1 | -0/+12 |
| 2024-07-17 | [RISCV] Don't fold vmerge.vvm or vmv.v.v into vredsum.vs if AVL changed (#99006) | Luke Lau | 1 | -5/+10 |
| 2024-07-09 | [RISCV] Allow folding vmerge into masked ops when mask is the same (#97989) | Luke Lau | 1 | -8/+23 |
| 2024-07-08 | [RISCV] Refactor mask check in performCombineVMergeAndVOps. NFC | Luke Lau | 1 | -3/+3 |
| 2024-07-06 | [RISCV] Allow folding vmerge with implicit passthru when true has tied dest (... | Luke Lau | 1 | -8/+0 |
| 2024-06-07 | [RISCV] Codegen support for XCVmem extension (#76916) | Liao Chunyu | 1 | -0/+74 |
| 2024-06-04 | Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149) | paperchalice | 1 | -3/+8 |
| 2024-06-02 | Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146) | paperchalice | 1 | -8/+3 |
| 2024-06-02 | [NewPM][CodeGen] Port selection dag isel to new pass manager (#83567) | paperchalice | 1 | -3/+8 |
| 2024-05-14 | [RISCV] Improve constant materialisation for stores of i8 negative constants ... | Alex Bradbury | 1 | -0/+5 |
| 2024-05-09 | [RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, ... | Craig Topper | 1 | -0/+13 |
| 2024-05-08 | [RISCV] Convert implicit_def tuples to noreg in post-isel peephole (#91173) | Luke Lau | 1 | -2/+9 |
| 2024-05-01 | [RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR ... | Luke Lau | 1 | -1/+7 |
| 2024-04-30 | [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions | Pengcheng Wang | 1 | -1/+0 |
| 2024-04-24 | [RISCV][NFC] Move RISCVMaskedPseudoTable to RISCVInstrInfo | Michael Maitland | 1 | -1/+0 |
| 2024-04-04 | [RISCV] Add patterns for fixed vector vwsll (#87316) | Luke Lau | 1 | -15/+15 |
| 2024-03-20 | [RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and G... | Craig Topper | 1 | -0/+37 |
| 2024-02-26 | [RISCV] Fix insert_subvector with fixed vector type creating invalid node (#8... | Luke Lau | 1 | -3/+5 |
| 2024-02-23 | [RISCV] Add asserts for insert/extract_subvector invariants. NFC | Luke Lau | 1 | -2/+6 |
| 2024-02-20 | [RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc] | Philip Reames | 1 | -3/+2 |
| 2024-02-06 | [RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variab... | Yeting Kuo | 1 | -6/+5 |
