| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-04-28 | [Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/6... | Craig Topper | 1 | -2/+2 |
| 2025-04-25 | [SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load... | Craig Topper | 1 | -1/+1 |
| 2024-12-12 | [RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to thei... | Craig Topper | 1 | -60/+0 |
| 2024-12-12 | [RISCV] Remove unused SDNodeXForm from RISCVGISel.td. NFC | Craig Topper | 1 | -9/+0 |
| 2024-12-06 | [RISCV] Add i16->i32 G_ZEXT/G_SEXT patterns for RV64. | Craig Topper | 1 | -6/+18 |
| 2024-12-05 | [RISCV][GISel] Use correct shift width for GIShiftMask32 ComplexOperandMatcher. | Craig Topper | 1 | -2/+2 |
| 2024-11-20 | [RISCV][GISel] Add atomic load/store test. Add additional atomic load/store i... | Craig Topper | 1 | -0/+13 |
| 2024-11-19 | [RISCV][GISel] Make extended loads and truncating stores with s16 register ty... | Craig Topper | 1 | -0/+3 |
| 2024-11-17 | [RISCV][GISel] Make loads/stores with s16 register type and s16 memory type l... | Craig Topper | 1 | -3/+31 |
| 2024-11-15 | [RISCV][GISel] Add isel patterns for i16 load/store (#116293) | Craig Topper | 1 | -6/+11 |
| 2024-11-14 | [RISCV][GISel] Remove most patterns that look for a zext i32->i64 and another... | Craig Topper | 1 | -10/+0 |
| 2024-11-14 | [RISCV][GISel] Remove isel pattern that is no longer tested after other recen... | Craig Topper | 1 | -6/+0 |
| 2024-11-13 | [RISCV][GISel] Promote s32 G_SEXTLOAD/ZEXTLOAD on RV64. | Craig Topper | 1 | -4/+0 |
| 2024-11-11 | [RISCV] Promote s32 G_SEXT_INREG for RV64 | Craig Topper | 1 | -5/+0 |
| 2024-11-11 | [RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559) | Craig Topper | 1 | -11/+6 |
| 2024-11-11 | [RISCV][GISel] Remove s32 support for G_ADD/SUB/AND/OR/XOR on RV64. | Craig Topper | 1 | -37/+0 |
| 2024-11-11 | [RISCV][GISel] Add i32 zext.h pattern for Zbkb. | Craig Topper | 1 | -0/+4 |
| 2024-11-11 | [RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64. | Craig Topper | 1 | -8/+0 |
| 2024-11-08 | [RISCV] Fix some isel patterns that used a type where we normally put a regcl... | Craig Topper | 1 | -1/+1 |
| 2024-11-08 | [RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEX... | Craig Topper | 1 | -7/+0 |
| 2024-11-08 | Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, ... | Craig Topper | 1 | -9/+0 |
| 2024-11-07 | [RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236) | Craig Topper | 1 | -0/+3 |
| 2024-11-07 | [RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107) | Craig Topper | 1 | -8/+0 |
| 2024-11-07 | [RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101) | Craig Topper | 1 | -4/+0 |
| 2024-11-06 | [RISCV][GISel] Add zexti8 ComplexPattern. | Craig Topper | 1 | -0/+2 |
| 2024-11-06 | Revert "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C... | Craig Topper | 1 | -0/+9 |
| 2024-11-06 | [RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns. (#115097) | Craig Topper | 1 | -0/+5 |
| 2024-11-04 | [GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309) | Craig Topper | 1 | -9/+0 |
| 2024-10-17 | [RISCV][GISel] Correct RORIW patterns. | Craig Topper | 1 | -1/+1 |
| 2024-10-04 | [RISCV][GISEL] instruction-select vmclr (#110782) | Michael Maitland | 1 | -0/+8 |
| 2024-10-03 | [RISCV][GISel] Remove some unneeded isel patterns. | Craig Topper | 1 | -179/+0 |
| 2024-10-01 | [RISCV][GISel] Stop promoting s32 G_SHL/ASHR/LSHR shift amount to s64 on RV64. | Craig Topper | 1 | -11/+10 |
| 2024-10-01 | [RISCV][GISel] Stop promoting s32 G_ROTL/ROTR rotate amount to s64 on RV64. | Craig Topper | 1 | -5/+7 |
| 2024-10-01 | Revert "[RISCV][GISel] Remove unused isel patterns for s32 shifts with s64 sh... | Craig Topper | 1 | -3/+7 |
| 2024-09-30 | [RISCV][GISel] Remove unused isel patterns for s32 shifts with s64 shift amount. | Craig Topper | 1 | -7/+3 |
| 2024-08-12 | [RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGIS... | Craig Topper | 1 | -0/+308 |
| 2023-12-04 | [RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825) | Craig Topper | 1 | -1/+9 |
| 2023-11-11 | [RISCV] Add an slli.uw pattern using zext for -riscv-experimental-rv64-legal-i32 | Craig Topper | 1 | -7/+0 |
| 2023-11-10 | [RISCV][GISel] Promote s32 constant shift amounts to s64 on RV64. | Craig Topper | 1 | -15/+0 |
| 2023-11-10 | [RISCV][GISel] Add isel patterns for SHXADD with s32 type on RV64. | Craig Topper | 1 | -0/+6 |
| 2023-11-01 | [RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32. | Craig Topper | 1 | -11/+0 |
| 2023-11-01 | [RISCV] Add experimental support for making i32 a legal type on RV64 in Selec... | Craig Topper | 1 | -46/+1 |
| 2023-10-26 | [RISCV][GISel] Allow G_AND/G_OR/G_XOR to have s32 types on RV64. | Craig Topper | 1 | -0/+10 |
| 2023-10-24 | [RISCV][GISel] Add ISel support for SHXADD_UW and SLLI.UW (#69972) | Min-Yih Hsu | 1 | -1/+17 |
| 2023-10-21 | [RISCV] Replace RISCV -> RISC-V in comments. NFC | Craig Topper | 1 | -1/+1 |
| 2023-10-18 | [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (#67863) | Min-Yih Hsu | 1 | -0/+7 |
| 2023-10-13 | [RISCV][GISel] Add isel patterns for ADDIW/SRLIW/SRAIW/SLLIW and remove custo... | Craig Topper | 1 | -1/+27 |
| 2023-10-10 | [RISCV][GlobalISel] Select G_ICMP, G_LOAD, G_STORE, G_ZEXTLOAD (#67619) | Nitin John Raj | 1 | -0/+100 |
| 2023-09-25 | [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG... | Min-Yih Hsu | 1 | -0/+8 |
| 2023-09-18 | [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64. | Craig Topper | 1 | -0/+1 |
