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path: root/llvm/lib/Target/RISCV/RISCV.h
AgeCommit message (Expand)AuthorFilesLines
2025-05-06Register assembly printer passes (#138348)Matthias Braun1-0/+2
2025-03-27[RISCV] Add late optimization pass for riscv (#133256)Mikhail R. Gadelha1-0/+3
2025-02-19Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into loa...Craig Topper1-0/+3
2025-02-19Revert "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/...Craig Topper1-3/+0
2025-02-19[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store ad...Craig Topper1-0/+3
2025-02-12[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 ...Luke Lau1-0/+3
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+2
2024-10-11[RISCV] Introduce VLOptimizer pass (#108640)Michael Maitland1-0/+3
2024-09-20Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"Michael Maitland1-3/+0
2024-09-19[RISCV] Add additional fence for amocas when required by recent ABI change (#...Alex Bradbury1-0/+3
2024-09-17[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)Michael Maitland1-0/+3
2024-08-08[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)Yeting Kuo1-0/+3
2024-08-06[RISCV] Insert simple landing pad for taken address labels. (#91855)Yeting Kuo1-0/+3
2024-07-11[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)Luke Lau1-2/+2
2024-07-10[GISel] Make create.*InstructionSelector arguments const (#98243)Michael Maitland1-3/+4
2024-06-04Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)paperchalice1-1/+1
2024-06-02Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)paperchalice1-1/+1
2024-06-02[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)paperchalice1-1/+1
2024-05-29[RISCV] Merge RISCVCoalesceVSETVLI back into RISCVInsertVSETVLI (#92869)Luke Lau1-3/+0
2024-05-16[RISCV] Defer creating RISCVInsertVSETVLI to avoid leak with -stop-after (#92...Luke Lau1-0/+1
2024-04-25Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vect...Luke Lau1-0/+3
2024-04-24Revert "[RISCV] Separate doLocalPostpass into new pass and move to post vecto...Luke Lau1-3/+0
2024-04-24[RISCV] Separate doLocalPostpass into new pass and move to post vector regall...Luke Lau1-0/+3
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-4/+0
2023-12-10[Target] Remove unused forward declarations (NFC)Kazu Hirata1-5/+0
2023-11-02[RISCV] Implement cross basic block VXRM write insertion. (#70382)Craig Topper1-0/+3
2023-10-30[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)Luke Lau1-0/+3
2023-10-25[RISCV] Add an experimental pseudoinstruction to represent a rematerializable...Craig Topper1-0/+2
2023-09-22[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67...Craig Topper1-0/+3
2023-09-20[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose ret...Yingwei Zheng1-0/+3
2023-09-18[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.Craig Topper1-0/+6
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks1-1/+1
2023-07-07[RISCV] Add a pass to combine `cm.pop` and `ret` instsWuXinlong1-0/+3
2023-06-21[RISCV] Add a pass to merge moving parameter registers instructions for ZcmpWuXinlong1-0/+3
2023-06-20[2/3][RISCV][POC] Model vxrm in LLVM intrinsics and machine instructions for ...eopXD1-0/+3
2023-06-12[RISCV] Merge RISCVMCInstLower.cpp into RISCVAsmPrinter.cpp.Craig Topper1-5/+0
2023-05-01[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.Craig Topper1-3/+0
2023-04-05[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperandPiyou Chen1-0/+3
2023-03-29[RISCV] Merge SExtWRemoval and StripWSuffix into a single pass.Craig Topper1-5/+2
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper1-1/+1
2023-02-22[RISCV] Add new pass to transform undef to pseudo for vector values.Piyou Chen1-0/+4
2023-02-15Revert D129735 "[RISCV] Add new pass to transform undef to pseudo for vector ...Fangrui Song1-4/+0
2023-02-14[RISCV] Add new pass to transform undef to pseudo for vector values.Piyou Chen1-0/+4
2022-12-22[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressi...Nitin John Raj1-0/+3
2022-12-21[llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining ...Nick Desaulniers1-4/+5
2022-07-31[RISCV] Pre-RA expand pseudos passLuís Marques1-0/+3
2022-07-14[RISCV] Add a RISCV specific CodeGenPrepare pass.Craig Topper1-0/+3
2022-05-30[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctlyeopXD1-1/+2
2022-05-25[RISCV] Add pre-emit pass to make more instructions compressibleLewis Revill1-0/+3
2022-05-01[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFCFangrui Song1-1/+1
generated by cgit v1.1 at 2025-08-03 23:37:51 +0000