aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/Disassembler
AgeCommit message (Expand)AuthorFilesLines
6 days[RISCV] Move definitions of decodeZcmpRlist/decodeXqccmpRlistS0 to their decl...Craig Topper1-23/+15
9 days[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructi...Craig Topper1-105/+6
2025-07-15[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)Jim Lin1-1/+2
2025-07-07[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)Jim Lin1-1/+2
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa1-0/+3
2025-07-01[RISCV] Use uint64_t for Insn in getInstruction32 and getInstruction16. NFC (...Craig Topper1-2/+6
2025-06-18[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension ...Jim Lin1-2/+2
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-05-21[RISCV] Add MC layer support for XSfmm*. (#133031)Craig Topper1-3/+36
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-0/+11
2025-05-15[RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (#139849)Jim Lin1-1/+2
2025-05-12[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (#138827)Jim Lin1-1/+2
2025-04-28[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)Jim Lin1-6/+9
2025-04-15[RISCV] Fix xmipscmov extension name (#135647)Djordje Todorovic1-2/+2
2025-04-04[RISCV] Make decodeXqccmpRlistS0 defer to decodeZcmpRlist after checking for ...Craig Topper1-4/+2
2025-04-04[RISCV] Remove unused function declaration. NFCCraig Topper1-3/+0
2025-04-04[RISCV] Rename Spimm to StackAdj in most places. NFCCraig Topper1-8/+2
2025-04-02[RISCV] Modify register type of extd* Xqcibm instructions (#134027)Sudharsan Veeravalli1-0/+10
2025-03-31[RISCV] Use decodeCLUIImmOperand when disassembling C_LUI_HINT. (#133789)Craig Topper1-8/+21
2025-03-31[RISCV] Correct disassembly of cm.push/pop for RVE. (#133816)Craig Topper1-6/+12
2025-03-31[RISCV] Prevent disassembling RVC hint instructions with x16-x31 for RVE. (#1...Craig Topper1-14/+24
2025-03-31[RISCV] Use decodeUImmLog2XLenNonZeroOperand in decodeRVCInstrRdRs1UImm. NFC ...Craig Topper1-15/+11
2025-03-31[RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#13...Paul Bowen-Huggett1-4/+8
2025-03-28[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)quic_hchandel1-9/+9
2025-03-28[RISCV] Remove unnecessary if guard before calling SignExtend64<6> in decodeC...Craig Topper1-2/+1
2025-03-28[RISCV] Fix the disassembler's handling of C.LUI when imm=0 (#133450)Paul Bowen-Huggett1-2/+3
2025-03-27[RISCV][Xqccmp] Correctly Parse/Disassemble pushfp (#133188)Sam Elliott1-1/+12
2025-03-26[RISCV] Use named sub-operands to simplify encoding/decoding for CoreV Reg-Re...Craig Topper1-12/+0
2025-03-22Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" ...Sudharsan Veeravalli1-8/+18
2025-03-21Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"Kazu Hirata1-18/+8
2025-03-22[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)quic_hchandel1-8/+18
2025-03-20[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996)quic_hchandel1-4/+4
2025-03-19[RISCV] Add Zilsd and Zclsd Extensions (#131094)dong-miao1-0/+16
2025-03-18[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)Sudharsan Veeravalli1-1/+2
2025-03-18[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)quic_hchandel1-6/+6
2025-03-17[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)Craig Topper1-10/+8
2025-03-13[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)u4f31-2/+3
2025-03-12[RISCV][Disassembler] Use a table to store all the decoder tables and their a...Craig Topper1-70/+100
2025-03-10[RISCV] Merge DecoderNamespace for CORE-V extensions. NFCCraig Topper1-14/+8
2025-03-10[RISCV] Merge DecoderNamespace for T-Head extensions. NFC (#130555)Craig Topper1-22/+10
2025-03-06[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)users/mariusz-sikora-at-amd/testquic_hchandel1-5/+27
2025-02-27[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)Craig Topper1-19/+13
2025-02-26[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)Sam Elliott1-1/+3
2025-02-26[RISCV][MC] Add assembler support for XRivosVisni (#128773)Philip Reames1-3/+6
2025-02-25[RISCV] Merge some of the Sifive decoder tables. (#128794)Craig Topper1-20/+13
2025-02-25[RISCV][NFC] Merge Xqci Decoder Tables (#128140)Sam Elliott1-28/+21
2025-02-25[RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)Sam Elliott1-0/+13
2025-02-24[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)quic_hchandel1-0/+2
2025-02-21[RISCV] Assembler support for XRivosVizip (#127694)Philip Reames1-0/+3
2025-02-21[RISCV] Simplify the debug messages in the disassembler. (#128102)Craig Topper1-78/+63
generated by cgit v1.1 at 2025-08-03 21:34:04 +0000