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path: root/llvm/lib/Target/RISCV/CMakeLists.txt
AgeCommit message (Expand)AuthorFilesLines
2025-07-11[RISCV][NFC] Split InterleavedAccess related TLI hooks into a separate file (...Min-Yih Hsu1-0/+1
2025-05-09[RISCV] TableGen-erate RISC-V SDNodes (#138381)Sam Elliott1-0/+1
2025-03-27[RISCV] Add late optimization pass for riscv (#133256)Mikhail R. Gadelha1-0/+1
2025-03-27[RISCV] Sort list of files. NFC.Mikhail R. Gadelha1-4/+4
2025-03-07[RISCV] Generate MIPS load/store pair instructions (#124717)Djordje Todorovic1-0/+1
2025-02-19Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into loa...Craig Topper1-0/+1
2025-02-19Revert "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/...Craig Topper1-1/+0
2025-02-19[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store ad...Craig Topper1-0/+1
2025-02-12[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 ...Luke Lau1-0/+1
2025-01-07[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)Craig Topper1-0/+1
2024-12-16[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (...Sergei Barannikov1-0/+1
2024-11-29[RISCV] Set a barrier between mask producer and user of V0 (#114012)Pengcheng Wang1-0/+1
2024-10-11[RISCV] Introduce VLOptimizer pass (#108640)Michael Maitland1-0/+1
2024-09-20Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"Michael Maitland1-3/+0
2024-09-19[RISCV] Add additional fence for amocas when required by recent ABI change (#...Alex Bradbury1-0/+1
2024-09-17[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)Michael Maitland1-0/+3
2024-09-09[RISCV] Support the large code model. (#70308)Jim Lin1-0/+1
2024-09-05[RISCV] Separate the calling convention handlers into their own file. NFC (#1...Craig Topper1-0/+1
2024-08-08[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)Yeting Kuo1-0/+1
2024-08-06[RISCV] Insert simple landing pad for taken address labels. (#91855)Yeting Kuo1-0/+1
2024-07-11[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)Luke Lau1-1/+1
2024-07-02[RISCV] Add the missing dependency on VectorizeMin Hsu1-0/+1
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-1/+0
2024-01-25[RISCV] Use TableGen-based macro fusion (#72224)Wang Pengcheng1-1/+1
2023-11-10[RISCV] Add missing component Scalar (#71905)Wang Pengcheng1-0/+1
2023-11-02[RISCV] Implement cross basic block VXRM write insertion. (#70382)Craig Topper1-0/+1
2023-10-30[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)Luke Lau1-0/+1
2023-10-25[RISCV] Add an experimental pseudoinstruction to represent a rematerializable...Craig Topper1-0/+1
2023-09-22[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67...Craig Topper1-0/+3
2023-09-20[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose ret...Yingwei Zheng1-0/+1
2023-09-18[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.Craig Topper1-0/+6
2023-09-15[RISCV][GlobalISel] Select ALU GPR instructionsCraig Topper1-1/+3
2023-08-28Revert "[RISCV][GlobalISel] Select ALU GPR instructions"Craig Topper1-3/+1
2023-08-28[RISCV][GlobalISel] Select ALU GPR instructionsCraig Topper1-1/+3
2023-07-07[RISCV] Add a pass to combine `cm.pop` and `ret` instsWuXinlong1-0/+1
2023-06-21[RISCV] Add a pass to merge moving parameter registers instructions for ZcmpWuXinlong1-0/+1
2023-06-20[2/3][RISCV][POC] Model vxrm in LLVM intrinsics and machine instructions for ...eopXD1-0/+1
2023-06-12[RISCV] Merge RISCVMCInstLower.cpp into RISCVAsmPrinter.cpp.Craig Topper1-1/+0
2023-05-03Split out `CodeGenTypes` from `CodeGen` for LLT/MVTNAKAMURA Takumi1-0/+1
2023-05-01[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.Craig Topper1-1/+0
2023-04-17[CMake] Reorder and reformat depsNAKAMURA Takumi1-2/+2
2023-04-05[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperandPiyou Chen1-0/+1
2023-03-29[RISCV] Merge SExtWRemoval and StripWSuffix into a single pass.Craig Topper1-2/+1
2023-02-22[RISCV] Add new pass to transform undef to pseudo for vector values.Piyou Chen1-0/+1
2023-02-15Revert D129735 "[RISCV] Add new pass to transform undef to pseudo for vector ...Fangrui Song1-1/+0
2023-02-14[RISCV] Add new pass to transform undef to pseudo for vector values.Piyou Chen1-0/+1
2022-12-22[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressi...Nitin John Raj1-0/+1
2022-12-20[Support] Move TargetParsers to new componentArchibald Elliott1-0/+1
2022-11-18[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCVMichael Maitland1-0/+1
2022-11-15Revert "[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate repor...Michael Maitland1-1/+0
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