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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.h
AgeCommit message (Expand)AuthorFilesLines
19 hours[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)Jeffrey Byrnes1-3/+0
2 days[LLVM][CodeGen][SVE2] Implement nxvf64 fpround to nxvbf16. (#111012)Paul Walker1-0/+1
2024-09-19[AArch64][NEON][SVE] Lower mixed sign/zero extended partial reductions to usd...Sam Tebbs1-1/+2
2024-09-16[AArch64] Expand scmp/ucmp vector operations with sub (#108830)David Green1-1/+1
2024-09-02[AArch64] Lower partial add reduction to udot or svdot (#101010)Sam Tebbs1-0/+3
2024-08-14[DAG] Support saturated truncate (#99418)hanbeom1-0/+5
2024-08-13[AArch64] Add lowering for `@llvm.experimental.vector.compress` (#101015)Lawrence Benson1-0/+2
2024-08-12[IA][AArch64]: Construct (de)interleave4 out of (de)interleave2 (#89276)Hassnaa Hamdi1-4/+6
2024-07-24[AArch64] Implement INIT/ADJUST_TRAMPOLINE (#70267)Carlos Seo1-0/+2
2024-07-22[AArch64][PAC] Sign block addresses used in indirectbr. (#97647)Ahmed Bougacha1-0/+1
2024-07-16[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of s...Volodymyr Vasylkun1-0/+2
2024-06-28[PAC][AArch64] Lower ptrauth constants in code (#96879)Daniil Kovalev1-0/+6
2024-06-27Revert "[PAC][AArch64] Lower ptrauth constants in code (#94241)" (#96865)Daniil Kovalev1-6/+0
2024-06-27[PAC][AArch64] Lower ptrauth constants in code (#94241)Daniil Kovalev1-0/+6
2024-06-26[CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (#88710)CarolineConcatto1-2/+1
2024-06-18[AArch64][SME] Remove unused ZA lazy-save (#81648)Matthew Devereau1-3/+6
2024-06-13[AArch64][SME] Save VG for unwind info when changing streaming-mode (#83301)Kerry McLaughlin1-0/+3
2024-05-31[AArch64][PAC] Lower authenticated calls with ptrauth bundles. (#85736)Ahmed Bougacha1-0/+12
2024-05-29[AArch64] Expand vector ops when NEON and SVE are unavailable. (#90833)Sander de Smalen1-2/+4
2024-05-13[AArch64] Add an all-in-one histogram intrinsicGraham Hunter1-0/+1
2024-05-10ISel/AArch64: custom lower vector ISD::[L]LRINT (#89035)Ramkumar Ramachandra1-0/+1
2024-04-27[AArch64] Lowering of fpmode intrinsics in DAG (#80611)Serge Pavlov1-0/+6
2024-04-24[AArch64] Unify lowering logic for fixed-length vectors. (#89393)Sander de Smalen1-1/+1
2024-04-15[LLVM][SelectionDAG] Allow verification of target ISD nodes. (#88121)Paul Walker1-0/+4
2024-04-05Prepend all library intrinsics with `#` when building for Arm64EC (#87542)Daniel Paoliello1-0/+3
2024-03-20[TTI][TLI][AArch64] Support scalable immediates with isLegalAddImmediate (#84...Graham Hunter1-0/+1
2024-03-15[AArch64] NFC: Simplify the smstart/smstop pseudo. (#85067)Sander de Smalen1-5/+5
2024-03-03[AArch64] Add more complete support for BF16David Majnemer1-0/+3
2024-03-01[AArch64] Remove unused AArch64ISD::BIT. NFCDavid Green1-3/+0
2024-02-22[AArch64] Switch to soft promoting half types. (#80576)Harald van Dijk1-0/+2
2024-01-31[AArch64][SVE2] Generate urshr rounding shift rights (#78374)Usman Nadeem1-0/+1
2024-01-31[SME] Stop RA from coalescing COPY instructions that transcend beyond smstart...Sander de Smalen1-1/+3
2024-01-22Arm64EC entry/exit thunks, consolidated. (#79067)Eli Friedman1-0/+5
2024-01-20[AArch64][SME2] Preserve ZT0 state around function calls (#78321)Kerry McLaughlin1-0/+2
2024-01-18[AArch64][SME] Conditionally do smstart/smstop (#77113)Matthew Devereau1-4/+4
2024-01-15[AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (#75832)chuongg31-0/+1
2023-12-05[CGP][AArch64] Rebase the common base offset for better ISelzhongyunde 004434071-0/+3
2023-12-02[AArch64] Stack probing for dynamic allocas in SelectionDAG (#66525)Momchil Velikov1-3/+10
2023-12-01[AArch64][SME] Remove implicit-def's on smstart (#69012)Jon Roelofs1-0/+3
2023-12-01[AArch64][SME2] Add SME2 builtins for zero { zt0 } (#72274)Matthew Devereau1-2/+2
2023-12-01[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#72849)Matt Devereau1-0/+2
2023-11-30[AArch64] Stack probing for function prologues (#66524)Momchil Velikov1-0/+10
2023-11-30[LLVM][SVE] Honour calling convention when using SVE for fixed length vectors...Paul Walker1-0/+12
2023-11-21[AArch64] Add SVE2.1 intrinsics for indexed quadword gather loads and scatter...Momchil Velikov1-0/+2
2023-11-21[AArch64][SVE2.1] Add intrinsics for quadword loads/stores with unscaled offs...Momchil Velikov1-0/+2
2023-11-20[AArch64][SME] Remove immediate argument restriction for svldr and svstr (#68...Sam Tebbs1-0/+4
2023-11-16Revert "[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795)"Matt Devereau1-2/+0
2023-11-14[CodeGen][AArch64] Set min jump table entries to 13 for AArch64 targets (#71166)David Sherwood1-0/+2
2023-11-14[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795)Matthew Devereau1-0/+2
2023-10-31[AArch64] Add intrinsic to count trailing zero elementsKerry McLaughlin1-0/+4
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