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7 days[RISCV] Implement MC support for Zvfbfa extension (#151106)Jim Lin1-0/+1
This patch adds MC support for Zvfbfa https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc Since Zvfbfa implies Zve32f, vector floating-point instructions can be used directly with Zvfbfa extension.
2025-08-18[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (#151706)林克1-0/+4
The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features): https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1 This patch only supports assembler.
2025-08-04[RISCV] Support resumable non-maskable interrupt handlers (#148134)Gergely Futo1-1/+1
The `rnmi` interrupt attribute value has been added for the `Smrnmi` extension. --------- Co-authored-by: Sam Elliott <sam@lenary.co.uk>
2025-07-15[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)Jim Lin1-0/+3
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. The extension includes only two instructions: one for converting from f32 to f16, and another for converting from f16 to f32. This patch only implements MC support for XAndesBFHCvt.
2025-07-07[RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)Jim Lin1-0/+3
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only implements MC support for XAndesVSIntLoad. --------- Co-authored-by: Lino Hsing-Yu Peng <linopeng@andestech.com>
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa1-0/+3
the extension enabled with xmipscbop. Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide" for more info on the extension at https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
2025-06-18[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension ↵Jim Lin1-0/+3
(#144320) The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. The instructions are similar to `Zvfbfmin` and the only difference with `Zvfbfmin` is that `XAndesVBFHCvt` doesn't have mask variant.
2025-06-16[RISCV] Xqccmp v0.3 (#137854)Sam Elliott1-1/+1
All the changes for v0.2 and v0.3 are either already implemented, or irrelevant to the compiler implementation.
2025-06-16[RISCV] Update Xqci to v0.13.0 (#144398)Sam Elliott1-17/+17
2025-06-16[RISCV] Change input register type for QC_SWM and QC_SWMI (#144294)Sudharsan Veeravalli1-1/+1
Version 0.13 of the `Xqci` spec changes the register type of input operand `rs3` from `GPR` to `GPRNoX0` for these two instructions. The spec can be found at https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0
2025-05-30[RISCV] Add shlcofideleg extension (#141572)Ying Chen1-0/+1
This is for `shlcofideleg` extension, that supports delegating LCOFI interrupts to VS-mode. Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc
2025-05-21[RISCV] Add MC layer support for XSfmm*. (#133031)Craig Topper1-0/+3
This adds assembler/disassembler support for XSfmmbase 0.6 and related SiFive matrix multiplication extensions based on the spec here https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification Functionality-wise, this is the same as the Zvma extension proposal that SiFive shared with the Attached Matrix Extension Task Group. The extension names and instruction mnemonics have been changed to use vendor prefixes. Note this is a non-conforming extension as the opcodes used here are in the standard opcode space in OP-V or OP-VE. --------- Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
2025-05-21[llvm] Fix typos in documentation (#140844)Kazu Hirata1-1/+1
2025-05-20[Docs][RISCV] Move Zilsd to 'Supported' status. NFC (#140757)Craig Topper1-1/+1
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-0/+1
Closes #130217. https://github.com/riscv/riscv-isa-manual/blob/main/src/q-st-ext.adoc
2025-05-15[RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (#139849)Jim Lin1-0/+3
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch.
2025-05-13[RISCV] Xqci Extensions v0.11.0 (#137881)Sam Elliott1-20/+20
This updates all the extensions to their version in the v0.11.0 spec. All changes from this version are already implemented or are not relevant to LLVM. This change also alphabetises the lists of Xqci extensions, to make future checks easier, and removes irrelevant info from the usage docs.
2025-05-12[RISCV][Docs] Correct links to Xmipscmov and Xmipslsp specifications. NFCCraig Topper1-2/+2
Need to add 2 underscores after the URL.
2025-05-12[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (#138827)Jim Lin1-0/+3
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch.
2025-05-07[RISCV] Fix the link to the XAndesPerf specification. NFC (#138804)Craig Topper1-1/+1
We need to use 2 underscores after the URL like the other specification links.
2025-04-28[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)Jim Lin1-0/+3
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Relocation and fixup for the branch and gp-implied instructions will be added in a later patch.
2025-04-25[RISCV] Add support for Ziccamoc (#136694)T-Tie1-1/+2
Support for Ziccamoc is added in this pr. Specification link: https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view --------- Co-authored-by: Tie <Tie@llvm.com>
2025-04-22[RISCV] Add smcntrpmf extension (#136556)Liao Chunyu1-0/+1
spec: https://github.com/riscvarchive/riscv-smcntrpmf
2025-04-15[RISCV] Fix xmipscmov extension name (#135647)Djordje Todorovic1-1/+1
The right name was used in riscv-toolchain-conventions docs.
2025-03-28[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)quic_hchandel1-0/+3
This extension adds two external input output instructions for non-memory-mapped device. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-22Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" ↵Sudharsan Veeravalli1-0/+3
(#132520) With a minor fix for the build failures. Original message: This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli quic_svs@quicinc.com
2025-03-21Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"Kazu Hirata1-3/+0
This reverts commit 3840f787a21a66686f5d8bf61877d41f3a65f205. Multiple builtbot failures have been reported: https://github.com/llvm/llvm-project/pull/132184
2025-03-22[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)quic_hchandel1-0/+3
This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-20[RISCV] Add assembler support for Zvqdotq. (#132118)Craig Topper1-0/+3
Based on the 0.0.1 spec here https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1
2025-03-20[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996)quic_hchandel1-0/+3
This extension adds two long branch instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-19[RISCV] Add Zilsd and Zclsd Extensions (#131094)dong-miao1-0/+2
This commit adds the Load/Store pair instructions (Zilsd) and Compressed Load/Store pair instructions (Zclsd). [Specification link](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc).
2025-03-18[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)Sudharsan Veeravalli1-0/+3
This extension adds 10 instructions that provide hints to the interface simulation environment. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/ This patch adds assembler only support.
2025-03-18[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)quic_hchandel1-0/+3
This extension adds twelve conditional branch instructions that use an immediate operand for the source. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-13[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)u4f31-0/+3
The Xqcili extension includes a two instructions that load large immediates than is available with the base RISC-V ISA. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support.
2025-03-11[RISCV] Update to Xqciint v0.4 (#130219)Sam Elliott1-1/+1
The Xqci 0.7.0 spec just came out, with some updates to Xqciint, bringing it to v0.4. The main update of any relevance is that `qc.c.mienter` and `qc.c.mienter.nest` now update both the stack pointer and the frame pointer (before, they only updated the stack pointer). They both remain compatible with the frame pointer convention. This change bumps the Xqciint version, and ensures that we don't emit the unneeded frame pointer adjustment instruction after `qc.c.mienter(.nest)`.
2025-03-06[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)users/mariusz-sikora-at-amd/testquic_hchandel1-0/+3
This extension adds thirty eight bit manipulation instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-02-26[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)Sam Elliott1-0/+3
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp instructions and reverse the order they push/pop registers in, which ends up matching the frame pointer convention. This extension adds a new instruction not present in Zcmp, `qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it has pushed the registers. This change duplicates the Zcmp implementation, with minor changes to mnemonics (for the `qc.` prefix), predicates, and the addition of `qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the specs are separate today. Specification: https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
2025-02-26[RISCV][Docs] RISCV -> RISC-V in RISCVUsage.rst. NFC (#128906)Craig Topper1-1/+1
2025-02-26[RISCV][MC] Add assembler support for XRivosVisni (#128773)Philip Reames1-0/+3
This implements assembler support for the XRivosVisni custom/vendor extension from Rivos Inc. which is defined in: https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvisni.adoc) Codegen support will follow in separate changes.
2025-02-26[RISCV] Xqcia 0.4 The spec was recently updated, this changes the name in ↵Luke Quinn1-1/+1
the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet. Signed-off-by: Luke Quinn <quic_lquinn@quicinc.com>
2025-02-25[RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (#128761)Philip Reames1-0/+3
There had been concern raised about possible confusion with "rvv". After internal discussion, we decided to go with an alternate prefix to reduce possible confusion going forward. The specification document (https://github.com/rivosinc/rivos-custom-extensions) has been updated. And also add the XRivosVizip extension to the documentation. I'd missed that in the initial commit.
2025-02-24[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)quic_hchandel1-0/+3
This extension adds eight 48 bit large arithmetic instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+6
Adding two extensions for MIPS p8700 CPU: 1. cmove (conditional move) 2. lsp (load/store pair) The official product page here: https://mips.com/products/hardware/p8700
2025-01-27[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)quic_hchandel1-1/+1
muliadd is more relevant to the operation performed, i.e. multiply by immediate. The latest spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest
2025-01-23[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)quic_hchandel1-0/+3
This extension adds eight 48 bit load store instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-13[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)quic_hchandel1-0/+3
This extension adds eleven instructions to accelerate interrupt servicing. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-07[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)quic_hchandel1-0/+3
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
2025-01-03[RISCV] Add support of Sdext,Sdtrig extentions (#120936)Shao-Ce SUN1-0/+3
`Sdext` and `Sdtrig` are RISC-V extensions related to debugging. The full specification can be found at https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
2025-01-03[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)Sudharsan Veeravalli1-0/+3
This extension adds 12 instructions that conditionally load an immediate value. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
2024-12-29[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension ↵quic_hchandel1-0/+3
(#121037) This extension adds 3 instructions that perform load-store address calculation. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com> Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
generated by cgit v1.1 at 2025-09-03 16:11:13 +0000