rocket-tools/riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-27	as: Add new estimated reciprocal instructions in LoongArch v1.1	Jiajie Chen	1	-0/+12
2023-11-27	as: Add new atomic instructions in LoongArch v1.1	Jiajie Chen	1	-0/+42
2023-11-24	RISC-V: drop leftover match_never() references	Jan Beulich	1	-4/+4
2023-11-24	x86: shrink opcode sets table	Jan Beulich	2	-2347/+302
2023-11-24	x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible	Jan Beulich	1	-0/+6
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-2/+2
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich	2	-45/+48
2023-11-24	Fix building for the s390 target with clang	Nick Clifton	1	-2/+3
2023-11-23	s390: Correct prno instruction name	Jens Remus	1	-1/+1
2023-11-23	s390: Add missing extended mnemonics	Jens Remus	2	-5/+31
2023-11-23	s390: Align optional operand definition to specs	Jens Remus	1	-9/+11
2023-11-23	s390: Make operand table indices relative to each other	Jens Remus	1	-82/+92
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+15
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+19
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+16
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	1	-0/+86
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	1	-0/+36
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+143
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	1	-0/+18
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+280
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+44
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma	1	-0/+4
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	1	-2/+12
2023-11-21	[opcodes] ARC + PPC: Fix -Walloc-size warnings	Jan-Benedict Glaw	2	-2/+2
2023-11-17	x86: CPU-qualify {disp16} / {disp32}	Jan Beulich	2	-3/+3
2023-11-16	aarch64: Add support for VMSA feature enhancements.	Srinath Parvathaneni	1	-0/+25
2023-11-16	aarch64: Add new AT system instructions.	Srinath Parvathaneni	1	-0/+9
2023-11-16	aarch64: Add support to new features in RAS extension.	Srinath Parvathaneni	1	-0/+14
2023-11-16	aarch64: Add features to the Statistical Profiling Extension.	Srinath Parvathaneni	1	-0/+1
2023-11-16	aarch64: Add SLC target for PRFM instruction.	Srinath Parvathaneni	1	-6/+6
2023-11-15	Finalized intl-update patches	Arsen Arsenovi?	7	-334/+2410
2023-11-10	Add support for ilp32 register alias.	Lulu Cai	2	-6/+6
2023-11-09	aarch64: Fix error in THE system register checking	Victor Do Nascimento	2	-4/+1
2023-11-09	x86: rework UWRMSR operand swapping	Jan Beulich	2	-3/+5
2023-11-09	x86: do away with is_evex_encoding()	Jan Beulich	2	-575/+585
2023-11-09	x86: split insn templates' CPU field	Jan Beulich	4	-474/+4249
2023-11-09	x86: Cpu64 handling improvements	Jan Beulich	3	-52/+90
2023-11-09	x86: Intel Core processors do not support CMPXCHG16B	Jan Beulich	2	-2/+2
2023-11-07	aarch64: Add LSE128 instructions	Victor Do Nascimento	4	-2407/+2558
2023-11-07	aarch64: Add arch support for LSE128 extension	Victor Do Nascimento	1	-0/+5
2023-11-07	aarch64: Add LSE128 instruction operand support	Victor Do Nascimento	3	-0/+8
2023-11-07	aarch64: Add 128-bit system register flags	Victor Do Nascimento	2	-10/+13
2023-11-07	aarch64: Add THE system register support	Victor Do Nascimento	3	-0/+10
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	2	-0/+39
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	2	-0/+37
2023-11-03	RISC-V: reduce redundancy in load/store macro insn handling	Jan Beulich	1	-19/+19
2023-11-02	aarch64: Add GCS system registers.	Srinath Parvathaneni	1	-0/+10
2023-11-02	aarch64: Add support for GCSB DSYNC instruction.	Srinath Parvathaneni	5	-2235/+2248
2023-11-02	aarch64: Add support for GCS extension.	srinath	4	-2510/+2559
2023-11-02	aarch64: Add support for Check Feature Status Extension.	Srinath Parvathaneni	2	-0/+11