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| author | Jan Beulich <jbeulich@suse.com> | 2023-11-09 12:53:30 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-11-09 12:53:30 +0100 |
| commit | 3eda60e3d6edfddf081ed2e8eb0901b6f6279413 (patch) | |
| tree | b4831b4b5ece5e6a06d8b92c92699f96c7ef9a1f /opcodes | |
| parent | cf5f570bd002fac5bc820d220d5cf8584cbaed6d (diff) | |
| download | gdb-3eda60e3d6edfddf081ed2e8eb0901b6f6279413.zip gdb-3eda60e3d6edfddf081ed2e8eb0901b6f6279413.tar.gz gdb-3eda60e3d6edfddf081ed2e8eb0901b6f6279413.tar.bz2 | |
x86: Intel Core processors do not support CMPXCHG16B
This being a 64-bit-only instruction (see also i386-opc.tbl) it cannot
possibly be supported by CPUs not supporting 64-bit mode.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-gen.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-init.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index bb58afc..b2ddda3 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -63,7 +63,7 @@ static const dependency isa_dependencies[] = { "NOCONA", "GENERIC64|FISTTP|SSE3|MONITOR|CX16" }, { "CORE", - "P4|FISTTP|SSE3|MONITOR|CX16" }, + "P4|FISTTP|SSE3|MONITOR" }, { "CORE2", "NOCONA|SSSE3" }, { "COREI7", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index d27c8b4..475db31 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -1541,7 +1541,7 @@ #define CPU_CORE_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |