[!] set Zephyr base address to 0x40000000 (was 0x10000000). bit-file is built successfully. Boot image coping is also OK (controlling via LED)

[*] go back to splitted PLL for system and DDR as in the MIG example. Trying to fix rd_clock constrain

simulation in modelsim successfully started (verification itself continue)

[!] hightick count reading value from GPTimer sim. bug fixed

[+] Zephyr successfully run on FPGA.
[!] UART registers mapping changed to fix bug with RX fifo reading on 128-bits bus.
[*] gnsslib submodules entirely excluded with porper config changing (no more test mode need)

[+] debug core register for RTL simulation module added

[+] vhdl: interaction with zephyr via uart during RTL simulation was implemented. Module uart_sim was added. Found exception 'unaligned store' on function unlock_irq(key) (fixing in progress).

[+] msvc 64-bits target added and proper fixes for implicit conversion size_t to int.
[*] header file with license related to risc-v were modified.

[*] FPGA ROM hex-image files were updated. Zephyr is now default application (fwimage.hex).

[!] Bug fixes: UART sim status, Simulator event queue removing item
[+] Bootloader updated to support mepc register saving

[!] GPTimers added to makefile
[+] Scripting support to debugger's console improved (add wait(msec) and input via uart0 serial)

Check for failed invocations which would cause the debugger to crash.

Correct dependencies in various makefiles. Add -g flags globally to detect
crash causes. Force listen command to use correct IP address. Inform if no
appropriate IP is available.

[!] Swap (cooperative/preemtive) methods updated with intlock flag.

[!] GPTimer emulator memory map fix accordingly with HW

[+] FW sources and images updated to support irq_lock register in irqctrl.
[!] Fix in _Swap assembler method

[+] context switching added

[+] script support added.
[+] gptimers simulation model added

zephyr: remove unused drivers&files, initial risc-v build success. _Swap method not implemented (just stub)