- Dec 04, 2020
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Anup Patel authored
There has been typo in automatic domain boot hart startup for non-root domains so this patch fixes it. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
We should check and access N-extension CSRs in sbi_hart_switch_mode() when next_mode is u-mode because N-extension is optional. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Dec 01, 2020
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Anup Patel authored
On RV32 systems, we have two CSRs for M-mode status (MSTATUS and MSTATUSH) when H-extension is implemented. This means we have to save/restore MSTATUSH for RV32 systems only when H-extension is implemented. The current _trap_handler() has extra instructions (roughly 10) for conditional save/restore of MSTATUSH CSR. These extra instructions in RV32 _trap_handler() can be avoided if we create separate low-level trap handler for RV32 systems having H-extension. This patch optimizes low-level trap handler for RV32 systems accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
The SBI SRST extension has been accepted and merged in the latest SBI v0.3-draft specification. (Refer, https://github.com/riscv/riscv-sbi-doc ) It allows to S-mode software to request system shutdown, cold reboot, and warm reboot. This patch implements SBI SRST extension as a replacement of the legacy sbi_shutdown() call of SBI v0.1 specification. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
To implement the SBI SRST extension, we need two platform operations for system reset: 1) system_reset_check() - This operation will check whether given reset type and reason are supported by the platform 2) system_reset() - This operation will do the actual platform system reset and it will not return if reset type and reason are supported by the platform This patch updates system reset related code everywhere as-per above. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Few platforms have dummy system reset functions so let's remove these dummy system reset functions to allow generic code deal with it in the right way. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
We can now use the standard SBI SRST extension reset types instead of the opensbi specific (SBI_PLATFORM_RESET_xyz) reset types hence remove related opensbi specific defines. The "platform_" prefix of the reset type parameter of sbi_system_reset() function should also be removed. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
We extend the SBI ecall interface header for the SBI SRST extension recently accepted in SBI specification v0.3-draft. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Nov 27, 2020
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Yuan Li authored
fix a typo error in docs/platform/sifive_fu540.md Signed-off-by:
Yuan Li <dskwelmcy@163.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Nov 10, 2020
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Anup Patel authored
Currently, we have all boot prints at the end of cold boot sequence which means if there is any failure in cold boot sequence before boot prints then we don't get any print. This patch improves boot prints in cold boot sequence as follows: 1. We divide the boot prints into multiple parts and print it from different locations after sbi_console_init() 2. We throw an error print if there is any failure in cold boot sequence after sbi_console_init() Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Nov 02, 2020
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Anup Patel authored
When PLATFORM_RISCV_ABI and PLATFORM_RISCV_ISA are not specified, we force "-mabi=lp64 -march=rv64gc" for RV64 and force "-mabi=ilp32 -march=rv32gc" for RV32. This can prevent users from using the toolchain default "-mabi" and "-march" options. To allow using toolchain defaults, we add compile-time option PLATFORM_RISCV_TOOLCHAIN_DEFAULT which when enabled forces the top-level makefile to use toolchain default ABI and ISA string. To enable the option, pass "PLATFORM_RISCV_TOOLCHAIN_DEFAULT=1" to top-level make. Reported-by:
Alistair Francis <alistair.francis@wdc.com> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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- Oct 27, 2020
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Atish Patra authored
We know about pmp granularity and number of bits supported by PMP. Show those information in the boot time info print Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Atish Patra authored
As per RISC-V privilege specification, a platform may choose to implement a coarser granularity scheme for PMP addresses. In that case, we shouldn't allow any pmp region size smaller than the platform supports. A platform may not also implement all the bits for a PMP address specified in the priv specification. The pmp range granularity and address bits should be detected dynamically before detecing PMP regions. Any pmp modification request beyond these detected value must not succeed. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Oct 23, 2020
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Atish Patra authored
The "reg" property in a device node may not be the correct address always. If a parent node defines a "ranges" property, the child address need to be translated with respect to parents address. If the ranges property is not present, it will just use 1:1 translation. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Oct 21, 2020
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Anup Patel authored
We add initial documentation for OpenSBI domain support to help RISC-V platform vendors achieve system-level partitioning. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
We extend boot prints to display details of each domain. In the process, we remove sbi_hart_pmp_dump() because it shows redundant information which domain details already show. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Oct 20, 2020
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Anup Patel authored
The PMP configuration on each HART should be only based on the memory regions of the assigned domain because each domain includes a memory region to protect the underlying firmware. This patch updates the sbi_hart_pmp_configure() function accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The sbi_hart_pmp_get() and sbi_hart_pmp_check_addr() functions are not used anymore hence this patch removes these functions. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The fdt_cpu_fixup() should disable a HART in DT if the HART is not assigned to the current HART domain. This patch updates fdt_cpu_fixup() accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Now that each HART is mapped to a domain having a set of memory regions, we update fdt_reserved_memory_fixup() to use domain memory regions for adding reserved memory nodes in device tree. We also change reserved memory node name prefix from "mmode_pmp" to "mmode_resv" because domain memory regions can impact other hardware configurations (such as IOPMP, etc) along with PMP. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The sbi_system_reset() should issue platform system reset only if domain of current HART is allowed to do system reset. This patch extends sbi_system_reset() as-per above. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Instead of calling sbi_hsm_hart_get_state() in a loop, we can simply call a new inline __sbi_hsm_hart_get_state() which only takes "hartid" and enforce domain checks using sbi_domain_assigned_hartmask(). This patch optimizes sbi_hsm_hart_started_mask() as-per above. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The sbi_hsm_hart_start() should consider the domain under which we are trying to start the HART. This will help ensure that HART A can start HART B only if both HARTs A and B belong to the same domain. We also have a special case when we bring-up boot HART of non-root domains in sbi_domain_finalize() where we should skip domain checks in sbi_hsm_hart_start(). To achieve this, sbi_hsm_hart_start() should do domain checks only when domain parameter is non-NULL. This patch extends sbi_hsm_hart_start() as-per above. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The sbi_hsm_hart_started_mask() API should take one more parameter to allow caller specify domain under which started_mask is being generated. Further, the sbi_hsm_hart_started_mask() depends on sbi_hsm_hart_get_state() which also should return HART state under specified domain. This patch updates both sbi_hsm_hart_started_mask() and sbi_hsm_hart_get_state() as-per above. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
An OpenSBI domain is a logical entity representing a set of HARTs and a set of memory regions for these HARTs. The OpenSBI domains support will allow OpenSBI platforms and previous booting stage (i.e. U-Boot SPL, Coreboot, etc) to partition a system into multiple domains where each domain will run it's own software. For inter-domain isolation, OpenSBI will eventually use various HW features such as PMP, ePMP, IOPMP, SiFive shield, etc but initial implementation only use HW PMP support. This patch provides initial implementation of OpenSBI domains where we have a root/default domain and OpenSBI platforms can provide non-root/custom domains using domain_get() callback. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The sbi_hartmask_test_hart() does not modify hartmask so the hartmask pointer parameter should be declared const. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
The hartid parameter of sbi_hart_init() is not used anywhere in sbi_hart_init() implementation so let's remove it. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
We factor-out PMP configuration from sbi_hart_init() as a separate sbi_hart_pmp_configure() function and do the PMP configuration very late in coldboot and warmboot path just before platform_final_init(). Eventually, this enable us to configure PMP totally based on OpenSBI domain where OpenSBI domains can be parsed from device-tree in any of the platform operations except platform_final_init(). Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
The pmp_region_xyz() callbacks are not required in sbi_platform_operations because we will be using OpenSBI domain memory regions to program the PMP CSRs. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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Anup Patel authored
The sbi_ecall.h and sbi_trap.h are not required to be included in sbi_platform.h hence we remove it. This way sources requiring these headers will have to explicitly include it thereby reducing implicit includes. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com>
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- Oct 18, 2020
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Anup Patel authored
The Kendryte K210 platform has built-in DTB and does not provides FW_PAYLOAD_FDT_ADDR. This means the FDT fixups will be done on the built-in DTB in absence of FW_PAYLOAD_FDT_ADDR. This patch adds some padding in built-in DTB for FDT fixups. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Heinrich Schuchardt authored
We extend d2c.sh to allow padding zeros in output C source when converting DTB to C source. Using this feature, platforms can create extra room for in-place FDT fixups on built-in DTBs. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The FW_PAYLOAD_FDT_PATH compile-time option is replaced by FW_FDT_PATH compile-time option which is more flexible and common across all OpenSBI firmwares. This patch removes FW_PAYLOAD_FDT_PATH and updates related documentation to use FW_FDT_PATH. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Currently, only FW_PAYLOAD has mechanism to embed external FDT using FW_PAYLOAD_FDT_PATH compile-time option. This patch adds a common FW_FDT_PATH compile-time option to embed external FDT for all OpenSBI firmwares (i.e FW_JUMP, FW_PAYLOAD, and FW_DYNAMIC). Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Currently, the make rules for ELF, BIN and LD script are little generic to allowing ELF, BIN and LD script to be anywhere in the build directory. For OpenSBI firmwares, the ELF, BIN, and LD script are always platform specific so we update make rules accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Oct 10, 2020
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Damien Le Moal authored
Add cleaning of compiled device tree files (.dtb files). Signed-off-by:
Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Oct 02, 2020
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Heinrich Schuchardt authored
%s/scatch/scratch Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Sep 25, 2020
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Pragnesh Patel authored
HiFive unleashed currently implements fewer than 56 bits of physical address so existing PMP CSR detection is broken. PMP address register encodes bits 55-2 of a 56-bit physical address, Not all physical address bits may be implemented, So just check minimum 1 bit. Fixes: 74d1db70 ("lib: sbi: Improve PMP CSR detection and progamming") Signed-off-by:
Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Sep 16, 2020
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Anup Patel authored
Currently, the generic platform fw_platform_init() marks non-MMU HARTs (e.g. E-core on SiFive Unleashed) as invalid. This means such non-MMU HARTs won't be allowed to go ahead by sbi_init(). The sbi_init() now has a check for next stage privilege mode when selecting coldboot HART. This check will force non-MMU HARTS (i.e. HARTs without S-mode) to proceed in warmboot path and wait in the HSM STOPPED state. This means we don't need to mark non-MMU HARTs as invalid in generic platform fw_platform_init(). Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The coldboot HART jumps to the next booting stage at the end of init_coldboot() so it is absolutely necessary for coldboot HART to support the privilege mode expected by the next booting stage. We extend the coldboot HART selection in sbi_init() to ensure that the selected coldboot HART always supports privilege mode specified in scratch space (i.e. scratch->next_mode). This will further help us allow E-core (without MMU) on SiFive Unleashed and PolarFire ICICLE boards to proceed further and wait in HSM STOPPED state. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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