This commit changes the MLIR to LLVMIR export to also attach subprogram
debug attachements to function declarations.
This commit addiitonally fixes the two passes that produce subprograms
to not attach the "Definition" flag to function declarations. This
otherwise results in invalid LLVM IR.

This patch fixes WebAssembly's FastISel pass to correctly consider
signext/zeroext parameter flags at function declaration.
Previously, the flags at call sites were only considered during code
generation, which caused an interesting bug report #63388 .
This is problematic especially because in WebAssembly's ABI, either
signext or zeroext can be tagged to a function argument, and it must be
correctly reflected in the generated code. Unit test
https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/WebAssembly/signext-zeroext.ll
shows that `i8 zeroext %t` and `i8 signext %t`'s code gen are different.

(42ec9761 was reverted by 26993f61 due to a use-after-scope bug.)

Reuse the patterns governing the previous input file being formatted if
the current input file is from the same directory.

* Add IRTranslate tests for ADD, SUB, AND, OR, and XOR with scalable
  vector types to show that they work as expected.
* Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR of scalable vector
  type for the RISC-V vector extension.

Move classes out of `let Predicates` scopes. The instantiation of the
class should be responsible for providing the Predicates.

Put the RV64 pseudoinstructions and patterns next to the RV32 version of
the same category. The categories are AMOs, pseudo AMOs, and compare
exchange. The main reason for this commit is that the compare exchange
patterns need to be disabled when Zacas is enabled so we can directly
select Zacas instructions with isel patterns. This necessitates compare
exchange having a different `let Predicates=` from the others anyway.

Similar to #76550, but for `ISD::AVGCEILU`.
Specifically, this patch aims to use `vaaddu` with rounding mode rnu
(i.e `vxrm[1:0] = 0b00`) for `ISD::AVGCEILU`.

### Source code 
```
define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
  %one = insertelement <vscale x 8 x i16> poison, i16 1, i32 0
  %splat = shufflevector <vscale x 8 x i16> %one, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
  %add1 = add nuw nsw <vscale x 8 x i16> %add, %splat
  %div = lshr <vscale x 8 x i16> %add1, %splat
  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
  ret <vscale x 8 x i8> %ret
}
```

### Before this patch 
```
vaaddu_vv_nxv8i8_ceil:
        vsetvli a0, zero, e8, m1, ta, ma
        vwaddu.vv       v10, v8, v9
        vsetvli zero, zero, e16, m2, ta, ma
        vadd.vi v10, v10, 1
        vsetvli zero, zero, e8, m1, ta, ma
        vnsrl.wi        v8, v10, 1
        ret
```
### After this patch 
```
vaaddu_vv_nxv8i8_ceil:
        vsetvli a0, zero, e8, m1, ta, ma
        csrwi vxrm, 0
        vaaddu.vv v8, v8, v9
        ret
```

Issue #77546

This reverts commit 07c9189f.

Issue #77546

This reverts commit b6d15770.

Fix various formatting issues in MyFirstTypoFix.

Reverts llvm/llvm-project#77441
I'll land it with fix.

`llvm.trap` is lowered to `PPC::TRAP` and `PPC::TRAP` is set as
terminator. Verifier complains about terminator should not lie in the
middle of an MBB. See #77095.

Fix it by removing `isTerminator` and `isBarrier` and then set `isTrap`
which was introduced by https://reviews.llvm.org/D48836# and is being
used by X86 and AArch64.

`PPC::TRAP` is not a hardware memory barrier and `llvm.trap` doesn't
indicate a memory barrier either.

This reverts commit 85f3d81fabb9381ce5bc0112d029a7c684b01006.

Affects BOLT macro-fusion and not NFC.

Invalid (direct) initializer would invalid `VarDecl` so
`InitializerScopeRAII` cannot restore scope stack balance.

As with other kind of initializer, `InitializerScopeRAII::pop()` is
moved up before `Sema::ActOnInitializerError()` which invalidates the
`VarDecl`, so scope can be balanced and current `DeclContext` can be
restored.

Fixes #30908

Shuffle can generate an array of unique and random numbers from 0 to
size-1. It can be used to generate tensors with specified sparsity
level.

It is desirable to be able to configure the `-mmacosx-version-min` flag
for the sanitizers, but this flag was never made a CACHE variable in
cmake.

By doing this, it will allow developers to select different minimum
versions, which results in different interceptors being enabled or
disabled on their platforms. This version can now persist between cmake
runs, so it can be remembered by cmake, and edited in the cache file.

llvm-project/mlir/test/lib/Dialect/Mesh/TestSimplifications.cpp:36:17:
 error: unused variable 'status' [-Werror,-Wunused-variable]
  LogicalResult status =
                ^
1 error generated.

The "kern ver str" LC_NOTE gives lldb a kernel version string -- with a
UUID and/or a load address (stext) to load it at. The LC_NOTE specifies
a size of the identifier string in bytes. In
ObjectFileMachO::GetIdentifierString, I copy that number of bytes into a
std::string, and in case there were additional nul characters at the end
of the sting for padding reasons, I tried to shrink the std::string to
not include these extra nul's.

However, I did this resizing without handling the case of an empty
identifier string. I don't know why any corefile creator would do that,
but of course at least one does. This patch removes the resizing
altogether; I was solving something that hasn't ever shown to be a
problem. I also added a test case for this, to check that lldb doesn't
crash when given one of these corefiles.

rdar://120390199

The death test infrastructure seems to depend on operator new, which
isn't currently supported in our hermetic tests. This patch just
disables the death tests in hermetic mode since they only overlap in the
nan tests.

Add overflow flags support to the following ops:
* `arith.addi`
* `arith.subi`
* `arith.muli`

Example of new syntax:
```
%res = arith.addi %arg1, %arg2 overflow<nsw> : i64
```
Similar to existing LLVM dialect syntax
```
%res = llvm.add %arg1, %arg2 overflow<nsw> : i64
``` 

Tablegen canonicalization patterns updated to always drop flags, proper
support with tests will be added later.

Updated LLVMIR translation as part of this commit as it currenly written
in a way that it will crash when new attributes added to arith ops
otherwise.

Discussion
https://discourse.llvm.org/t/rfc-integer-overflow-flags-support-in-arith-dialect/76025



---------

Co-authored-by: Yi Wu <yi.wu2@arm.com>

The main motivations behind this are two:

- Allow different companies developing their own vscode extensions for
LLDB to have a single contribution point, thus sharing resources and
working as a virtual large team.
- Allow for visual ways to configure the debugger, which currently has
to be done through launch.json files.

In terms of implementation, this is very straightforward and these are
the most important details:

- All the cpp code has been moved to a subfolder for cleanness. There's
a specific commit in the list of commits of this PR that just does that,
in case that helps reviewing this.
- A new folder `src-ts` has been created for the typescript code
- The ts extension can be used in two ways: as a regular vscode
extension and as a library. There file `extension.ts` explains which
entry point to use.
- The README has been updated the mention how to install the extension,
which is simpler than before. There are tw...

Instead of using a concept defined in the internal implementation, use a
definition of the simple_view ranges concept separately defined and
included in test code.

Summary contains one line and should point to user code instead of
internal compiler-rt location. TSAN already does that.

Mark `.lcovmap$M`, `.lcovfun$M`, `.lcovd` and `.lcovn` as metadata
sections on COFF so they are not loaded into memory.

If the mesh has static size on some of the requested axes, the result is
substituted with a constant.

Fixes #77517

Prior to this commit, it was impossible to use the simple string
matching directives to look for any content that contains unbalanced
`{{` `}}` pairs, such as:

```
// expected-note {{my_struct{{1}, 2}}}
```

Which would parse like so:

```
             "nested" brace v
// expected-note {{my_struct{{1}, 2}}}
          closes the nested brace  ^ |
                            trailing }
```

And the frontend would complain 'cannot find end ('}}') of expected'.

At this snapshot, VerifyDiagnosticConsumer's parser now counts the
opening braces and looks for a matching length of closing sigils,
allowing the above to be written as:

```
// expected-note {{{my_struct{{1}, 2}}}}
   opening brace |-|                 |-|
  closing brace is '}}}', found here ^
```

This came about as a result of this discussion:
https://github.com/llvm/llvm-project/pull/74852#discussion_r1443117644

cc @erichkeane

LLVM assumes round-to-nearest mode and sometimes performs constant-folding based on that assumption. This updates the language ref documentation for the rint and nearbyint intrinsics to mention that fact.

This patch fixes:

  lldb/source/Target/ProcessTrace.cpp:23:33: error: extra ';' outside
  of a function is incompatible with C++98
  [-Werror,-Wc++98-compat-extra-semi]

This patch adds an intrinsic for setmaxnreg PTX instruction.
* PTX Doc link for this instruction:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-setmaxnreg



* The i32 argument, an immediate value, specifies the actual
  absolute register count for the instruction.
* The `setmaxnreg` instruction is available in SM90a.
  So, this patch adds 'hasSM90a' predicate to use in
  the NVPTX backend.
* lit tests are added to verify the lowering of the intrinsic.
* Verifier logic (and tests) are added to test the register
  count range and divisibility-by-8 requirements.

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

Summary:
The CPU targets currently rely on `libffi` to invoke the "kernel"
functions. Previously we would not build these if this dependency was
not found. This patch copies th eapproach used for things like CUDA and
HSA to dynamically load this if it is not found.

The one sketchy thing this does is hard-code the default ABI for the
target. These are normally defined on a per-file basis in the FFI
source, so I had to fish out the expected values. We only use two types,
so ideally we will always be able to use the default ABI.

It's possible we could remove this dependency entirely in the future as
well.

https://github.com/llvm/llvm-project/pull/76471 introduced a new test
but the check lines have over-restrictive patterns for a string variable
name that cause test failures on Windows (e.g.
https://lab.llvm.org/buildbot/#/builders/127/builds/60637/steps/4/logs/stdio).
This PR fixes the test.

The test sets `-mtriple=x86_64` but doesn't require it. This can cause issue on
non-x86 system.

This was causing compilation errors when attempting to compare a
`shared_ptr<T[]>` with `nullptr`, as `get()` returns `T*` rather than `T
(*)[]`. `unique_ptr` did not have this issue, but I've added tests to
make sure.

Using `regex_search` with the regex_constant `match_default` and a
simple regex pattern `$` is expected to match general strings such as
_"a", "ab", "abc"..._ at `[last, last)` positions. But, the current
implementation fails to do so.

Fixes #75042

Regarding
```
.option norelax
j label
.option relax
// relaxable instructions
// For assembly input, RISCVAsmParser::ParseInstruction will set ForceRelocs (https://reviews.llvm.org/D46423).
// For direct object emission, ForceRelocs is not set after https://github.com/llvm/llvm-project/pull/73721
label:
```

The J instruction needs a relocation to ensure the target is correct
after linker relaxation. This is related a limitation in the assembler:
RISCVAsmBackend::shouldForceRelocation decides upfront whether a
relocation is needed, instead of checking more information (whether
there are relaxable fragments in between).

Despite the limitation, `j label` produces a relocation in direct object
emission mode, but was broken by #73721 due to the shouldForceRelocation
limitation.

Add a workaround to RISCVTargetELFStreamer to emulate the previous
behavior.

Link: https://github.com/ClangBuiltLinux/linux/issues/1965