Created using spr 1.3.5-bogner

Created using spr 1.3.5-bogner

This is the insert_subvector equivalent to #79949, where we can avoid
sliding up by the full LMUL amount if we know the exact subregister the
subvector will be inserted into.

This mirrors the lowerEXTRACT_SUBVECTOR changes in that we handle this
in two parts:

- We handle fixed length subvector types by converting the subvector to
a scalable vector. But unlike EXTRACT_SUBVECTOR, we may also need to
convert the vector being inserted into too.

- Whenever we don't need a vslideup because either the subvector fits
exactly into a vector register group *or* the vector is undef, we need
to emit an insert_subreg ourselves because RISCVISelDAGToDAG::Select
doesn't correctly handle fixed length subvectors yet: see d7a28f7a

A subvector exactly fits into a vector register group if its size is a
known multiple of the size of a vector register, and this adds a new
overload for TypeSize::isKnownMultipleOf for scalable to scalable
comparisons to help reason about this.

I've left RISCVISelDAGToDAG::Select untouched for now (minus relaxing an
invariant), so that the insert_subvector and extract_subvector code
paths are the same.

We should teach it to properly handle fixed length subvectors in a
follow-up patch, so that the "exact subregsiter" logic is handled in one
place instead of being spread across both RISCVISelDAGToDAG.cpp and
RISCVISelLowering.cpp.

- Adds a status page note for P3142R0
- Fixes a copy & paste error in tuple protocol for `complex`

Fixes https://github.com/llvm/llvm-project/issues/89668

Ensure it's clear that:

- Infinite loops in non-mustprogress functions are well-defined, even if
they're called by mustprogress functions.
- Infinite recursion in mustprogress functions is not well-defined.

Looking at D86233, it's clear this was the intent, but the "transitive"
wording is ambiguous. Instead, just explicitly state that infinite loops
written in non-mustprogress functions count as progress.

Expand `arith.minsi`, `arith.minui`, `arith.maxsi`, `arith.maxui` into
`arith.cmpi` and `arith.select`.

---------

Co-authored-by: Jakub Kuderski <kubakuderski@gmail.com>

Forgot to add vp.cttz.elts into the unittest. Also, I didn't specify the
positions of overloaded type parameters.

Return an SDValue instead of pushing to the Results vector. Let
the caller do the push.

This will unify the interface a bit more.

… NFC

We were always calling SDLoc(N) at the top of each visitSHL/SRL/SRA for the FoldConstantArithmetic call, so just reuse this as much as possible.

Based off #90355 - add basic tests for cases when to extend i16 comparisons to i32

This patch generalizes tensor.expand_shape and memref.expand_shape to
consume the output shape as a list of SSA values. This enables us to
implement generic reshape operations with dynamic shapes using
collapse_shape/expand_shape pairs.

The output_shape input to expand_shape follows the static/dynamic
representation that's also used in `tensor.extract_slice`.

Differential Revision: https://reviews.llvm.org/D140821



---------

Signed-off-by: Gaurav <Shukla&lt;gaurav.shukla@amd.com>
Signed-off-by: Gaurav Shukla <gaurav.shukla@amd.com>
Co-authored-by: Ramiro Leal-Cavazos <ramiroleal050@gmail.com>

This intrinsic is the VP version of `experimental.cttz.elts`.

We might use polymorphic ops in top-level operations other than
functions some time in the future. We need to ensure that these
operations can be lowered.

See RFC:

https://discourse.llvm.org/t/rfc-add-an-interface-for-top-level-container-operations

Some of the changes are from moving declaration and definition of the
constructor function into tablegen (as requested in code review when
altering another pass).

Before this patch we crashed lowering intrinsic array reductions.

I think this lost during a rebase. I've added a test to make sure it
doesn't break again.

Also fixed the TODO message to be more accurate.

[AMPGPU] Emit s_singleuse_vdst instructions when a register is used multiple times in the same instruction. (#89601)

Previously, multiple uses of a register within the same instruction were
being counted as multiple uses. This has been corrected to
only count as a single use as per the specification allowing for
more optimisation candidates.

This reverts commit 9d5411ff.

Breaks aarch64 buildbot:
https://lab.llvm.org/buildbot/#/builders/221/builds/22130

Previously we weren't printing expressions correctly, so this patch adds
a test to ensure we do, and fixes how expressions are printed.

COPY operands are always registers.

This patch introduces fir.cuda_alloc/fir.cuda_free. These operations
will be used instead of fir.alloca for local CUDA device, managed and
unified variables.

Store of the current induction value to the user IV was not placed
correctly in the body of the cuf kernel.

@ImanHosseini

This replaces some starts_with calls wth consume_front. This allows us
to remove a later assumption that prefix was 4 characters. We would
eventually need to fix this anyway if we ever support rv128.

Noticed while reviewing the RISCVISAInfo code for other reasons.

Enable MachineCombining for FP add, sub and mul.

In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.

Added support for memref-normalization for prefetch.

Signed-off-by: Alexandre Eichenberger <alexe@us.ibm.com>

This reverts commit 6c311046.

Required by the post commit comments: https://github.com/llvm/llvm-project/pull/86912

When compiling for thumbv8.1m with +pacbti and making an indirect tail
call, the compiler was free to put the function pointer into R12.

This is incorrect because R12 is restored to contain authentication code
for the caller's return address.

This patch excludes R12 from the set of registers the compiler can put
the function pointer in.

Fixes https://github.com/llvm/llvm-project/issues/75998

Reverts llvm/llvm-project#90497
Broke some LLD tests.