This patch completes the support for EBCDIC I/O support on z/OS using the autoconversion functions.

As part of the RemoveDIs project, transitioning to non-instruction debug
info, all debug intrinsic handling code needs to be duplicated to handle
DPValues.

--try-experimental-debuginfo-iterators enables the new debug mode in
tests if the CMake option has been enabled.

`getInsertPtAfterFramePtr` now returns an iterator so we don't lose
debug-info-communicating bits.

---

Depends on #73500, #74090, #74091.

They're duplicated with

llvm/test/MC/X86/avx512vp2intersect-32-intel.s
llvm/test/MC/X86/avx512vp2intersect-64-intel.s

Deletes slots that have lifetime markers and the lifetime ranges are
empty.

This is a follow-up on [PR
75218](https://github.com/llvm/llvm-project/pull/75218) that avoids
reconstructing a fused loc in the `FlattenFusedLocationRecursively`
helper when there has been no change.

This reverts commit 2684281d.

Due to being flaky on Arm and AArch64 buildbots.

These are intrinsics are only used ephemerally and be should be given a
zero cost.

[reland][libc][NFC] Implement `FPBits` in terms of `FloatProperties` to reduce clutter (#75196) (#75318)

Also make type naming consistent by using `UIntType` instead of
`intU_t`.
This patch is a reland of #75196 but does not include the "use `FPBits`
instead of `FPBits_t`, `FPB`" part. This needs more work.

Note that all the patches that implement support for declare-style
DPValues have tests that are "rotten green" test without this
patch (i.e., they pass at the moment without testing what we
want them to test). See the Pull Request for more detail on this.

Pass MemoryLocation as one argument, instead of passing all its
parts separately.

... for a potential constant expression. They are not defined now, but
might be defined later when the function is actually called.

This is a fix for 96ab8ef9

This bit was added to the AArch64 ABI by
https://github.com/ARM-software/abi-aa/pull/231.

.00cfg section is used by crt for load config and is merged by MS
link.exe into .rdata.

Fixes #75002. Found while running libc++'s tests with MSVC's STL.

This is a superset of #74961 that also fixes the product code
and adds a regression test. Thanks again, @cpplearner!

To summarize: `views::split` and `views::lazy_split` aren't unary,
aren't range adaptor **closure** objects, and can't be piped. However,
\[range.adaptor.object\]/8 says that `views::split(pattern)` and
`views::lazy_split(pattern)` produce unary, pipeable, range adaptor
closure objects.

This PR adjusts the test coverage accordingly, allowing it to portably
pass for libc++ and MSVC's STL.

[mlir][ArmSME][test] Use `only-if-required-by-ops` rather than `enable_arm_streaming_ignore` (NFC) (#75209)

This moves the fix out of the IR and into the pass description, which
seems nicer. It also works as an integration test for the
`only-if-required-by-ops` flag :)

Inject missing dependency between generated files that could cause build
issues.

Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>

This adds a link from the main docs page back to the README where
I have previously added a list of useful resources.

To that list, I've added a link to my recent llvm blog post.

This commit ensures that we model DI information for global constants
correctly. These constructs can lack scopes, names, and linkage names,
so these parameters were made optional for the DIGlobalVariable
attribute.

The disallowlist was used as a migration strategy while support was
extended to more side effecting operations. We now (to the best of our
knowledge) support all side effecting operations, so never fail
`isLegalToInline` on any LLVM operation.

There is no test included, because that's exactly the reason for this
change: there are no more unsupported operations in inlining; the
existing tests for unsupported inlines have already been burninated.

fix #72114
proof: https://alive2.llvm.org/ce/z/xqprFm

When doing sink-and-fold, the MachineSink clears the "killed" flags of
the operands of the sunk (and deleted) instruction. However, this is not
always sufficient. In some cases we can create the new load/store
instruction with operands other than the ones present in the deleted
instruction. One such example is folding a zero word extend into a
memory load on AArch64. The zero-extend is represented by a pair of
instructions - `MOV` (i.e. `ORRwrs`) followed by a `SUBREG_TO_REG`. The
`SUBREG_TO_REG` is deleted (it is the sunk instruction), but the new
load instruction mentions operands "killed" in the `MOV`, which is no
longer correct.

To fix this, clear the "killed" flags of the registers participating in
the addressing mode.

Fix unexpected pass after
https://github.com/llvm/llvm-project/pull/74786.