1. Jan 07, 2022
    • Craig Topper's avatar
      [RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics. · ec4dd862
      Craig Topper authored
      The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing
      the immediate. To prevent his we had special patterns that provided
      alternate lowering for the 0 cases. This relied on tablegen prioritizing
      the 0 pattern over the sim5_plus1 range.
      
      This patch introduces simm5_plus1_nonzero that excludes 0. It also
      excludes the special case for vmsltu.vi since we can just use
      vmsltu.vx and let the 0 be selected to X0.
      
      This is an alternative to some of the changes in D116584.
      
      Reviewed By: Chenbing.Zheng, asb
      
      Differential Revision: https://reviews.llvm.org/D116723
      ec4dd862
    • Jake Egan's avatar
      [CMake] Include ZLIB_ROOT in LLVMConfig.cmake · e3a26183
      Jake Egan authored
      Include the value of `ZLIB_ROOT` in `LLVMConfig.cmake` so `FindZLIB` can pick it up. This fixes an issue where ZLIB is not found on AIX runtimes despite specifying `-DZLIB_ROOT`.
      
      Reviewed By: daltenty
      
      Differential Revision: https://reviews.llvm.org/D116235
      e3a26183
    • Craig Topper's avatar
      [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies. · 56ca11e3
      Craig Topper authored
      Function calls and compare instructions tend to cause sext.w
      instructions to be inserted. If we make good use of W instructions,
      these operations can often end up being redundant. We don't always
      detect these during SelectionDAG due to things like phis. There also
      some cases caused by failure to turn extload into sextload in
      SelectionDAG. extload selects to LW allowing later sext.ws to become
      redundant.
      
      This patch adds a pass that examines the input of sext.w instructions trying
      to determine if it is already sign extended. Either by finding a
      W instruction, other instructions that produce a sign extended result,
      or looking through instructions that propagate sign bits. It uses
      a worklist and visited set to search as far back as necessary.
      
      Reviewed By: asb, kito-cheng
      
      Differential Revision: https://reviews.llvm.org/D116397
      56ca11e3
    • Evgeny Mandrikov's avatar
      Fix build failure with GCC 11 in C++20 mode · 2ccf0b76
      Evgeny Mandrikov authored
      See https://wg21.link/cwg2237
      
      Reviewed By: shafik, dexonsmith
      
      Differential Revision: https://reviews.llvm.org/D115355
      2ccf0b76
    • Craig Topper's avatar
      [RISCV] Don't advertise i32->i64 zextload as free for RV64. · 75117fb3
      Craig Topper authored
      The zextload hook is only used to determine whether to insert a
      zero_extend or any_extend for narrow types leaving a basic block.
      Returning true from this hook tends to cause any load whose output
      leaves the basic block to become an LWU instead of an LW.
      
      Since we tend to prefer sexts for i32 compares on RV64, this can
      cause extra sext.w instructions to be created in other basic blocks.
      
      If we use LW instead of LWU this gives the MIR pass from D116397
      a better chance of removing them.
      
      Another option might be to teach getPreferredExtendForValue in
      FunctionLoweringInfo.cpp about our preference for sign_extend of
      i32 compares. That would cause SIGN_EXTEND to be chosen for any
      value used by a compare instead of using the isZExtFree heuristic.
      That will require code to convert from the llvm::Type* to EVT/MVT
      as well as querying the type legalization actions to get the
      promoted type in order to call TargetLowering::isSExtCheaperThanZExt.
      That seemed like many extra steps when no other target wants it.
      Though it would avoid us needing to lean on the MIR pass in some cases.
      
      Reviewed By: asb
      
      Differential Revision: https://reviews.llvm.org/D116567
      75117fb3
    • Craig Topper's avatar
      [RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand. · 808c6626
      Craig Topper authored
      Pre-work for a future change that will use these opcodes with other
      rounding modes.
      
      Differential Revision: https://reviews.llvm.org/D116724
      808c6626
    • Nikita Popov's avatar
      [EarlyCSE] Support opaque pointers · 918015c9
      Nikita Popov authored
      Explicitly check the load/store value type, because this is no
      longer implicitly checked through the pointer type.
      918015c9
    • Simon Pilgrim's avatar
      [AST] ASTContext::mergeTypes - pull out repeated getAs<> calls. NFC. · e3e8799b
      Simon Pilgrim authored
      Avoids static-analyzer null dereference warnings.
      e3e8799b
    • Matt Arsenault's avatar
      AMDGPU: Clear NoPHIs property in SIOptimizeVGPRLiveRanges · 4fc18de3
      Matt Arsenault authored
      Fixes verifier error when writing MIR tests that didn't have phis to
      begin with.
      4fc18de3
  2. Jan 06, 2022