In D146245, we have supported lowering inline asm `m` with offset
to `register+imm`, but we didn't handle the case that the offset
is the low part of global address.

This patch will emit `%lo(g)` when `g` is a global address.

Fixes #64656

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D157839

We will need to check the output of medium code model.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D157965

This will represent functions with the amdgpu_cs_chain or
amdgpu_cs_chain_preserve calling conventions.

Differential Revision: https://reviews.llvm.org/D156410

Add support for following vector to tile (MOVA) intrinsics to ArmSME
dialect:

  llvm.aarch64.sme.write.vert
  llvm.aarch64.sme.write.horiz

Includes the definition of new type predicate
'ScalableVectorOfRankAndLengthAndType' in OpBase.td.

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D157004

D152276 wasn't handling the case where the inserted element is implicitly truncated into the vector - resulting in a i1 element (implicitly truncated from i8) overwriting 8 bits instead of 1 bit.

This patch is intended to be merged into 17.x so I've just disallowed any vector element vs inserted element type mismatch - technically we could be more elegant and permit truncated stores (as long as the store is still byte sized), but the use cases for that are so limited I'd prefer to play it safe for now.

Candidate patch for #64655 17.x merge

Differential Revision: https://reviews.llvm.org/D158366

In preparation for their removal in D158081.

This method is only used to determine whether a related expansion
exists, the actual value is unused. Clarify that by renaming
get -> has and returning bool.

Fold (-a >> b) and/or/xor (~a >> b) into (-a and/or/xor ~a) >> b.
Depends on D157289.

Differential Revision: https://reviews.llvm.org/D157290

Precommit tests for D157290.

Differential Revision: https://reviews.llvm.org/D157289

The x86_64 SysV ABI specifies that __int128 is passed either in
two registers (if available) or in a 16 byte aligned stack slot.
GCC implements this behavior. However, if only one free register
is available, LLVM will instead pass one half of the i128 in a
register, and the other on the stack.

Make sure that either both are passed in registers or both on the
stack.

Fixes https://github.com/llvm/llvm-project/issues/41784.
The patch is basically what craig.topper proposed to do there.

Differential Revision: https://reviews.llvm.org/D158169

Previously `M-x mark-defun` and friends wouldn't work properly, and would
highlight something at the top of the buffer. This adds a regexp for top-level
functions so the defun functions should work as expected, and also adds a
regexp for extracting their name so which-function-mode should work now too.

Reviewed By: goldstein.w.n

Differential Revision: https://reviews.llvm.org/D158196

Restore the desired setting that was reverted in

  https://reviews.llvm.org/D158289.

This is to be merged once Fortran tests in llvm-test-suite are updated
accordingly:

  https://reviews.llvm.org/D158308.

Differential Revision: https://reviews.llvm.org/D158307

Lower formal arguments and returns for functions with the
`amdgpu_cs_chain` and `amdgpu_cs_chain_preserve` calling conventions:

* Put `inreg` arguments into SGPRs, starting at s0, and other arguments
into VGPRs, starting at v8. No arguments should end up on the stack, if
we don't have enough registers we should error out.

* Lower the return (which is always void) as an S_ENDPGM.

* Set the ScratchRSrc register to s48:51, as described in the docs.

* Set the SP to s32, matching amdgpu_gfx. This might be revisited in a
future patch.

Differential Revision: https://reviews.llvm.org/D153517

This patch is extracted from D96035, it adds support for the existing
DWARFLinker functionality. What is not supported yet:

1. Types deduplication(--odr mode).
2. Modules deduplication.
3. Generation of index tables.

Reland2: temporarily disabled call to "--linker llvm" for tls-variable.test
and location-expression.test as it does not work properly on bigendian
architecture.

Differential Revision: https://reviews.llvm.org/D153268

Prior to this change clang didn't emit missing-field-initializers
warning for designated initializers. The comments say that it is done to
match gcc behavior. However, gcc behaves so only for C. For C++ warnings
are emitted.

Fixes https://github.com/llvm/llvm-project/issues/56628

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D157879

Expand (s/z/any)ext instructions to be compatible with more
types for GlobalISel.
This patch mainly focuses on 64-bit and 128-bit vectors with
element size of powers of 2.
It also notably handles larger than legal vectors.

Differential Revision: https://reviews.llvm.org/D157113

This reverts commit 0229dd06.

This introduces two test failures on s390x.

tools/dsymutil/X86/location-expression.test:

    warning: cann't load line table.
    note: while processing CU1
    /builddir/build/BUILD/llvm-18.0.0.src/test/tools/dsymutil/X86/location-expression.test:20:10: error: CHECK: expected string not found in input
    # CHECK: DW_AT_name{{.*}}"CU1"
             ^
    <stdin>:34:32: note: scanning from here
    0x0000000b: DW_TAG_compile_unit [1] *
                                   ^
    <stdin>:37:2: note: possible intended match here
     DW_AT_name [DW_FORM_strp] ( .debug_str[0x09000000] = )
     ^

tools/dsymutil/X86/tls-variable.test:

    warning: cann't load line table.
    note: while processing CU1
    /builddir/build/BUILD/llvm-18.0.0.src/test/tools/dsymutil/X86/tls-variable.test:19:10: error: CHECK: expected string not found in input
    # CHECK: DW_AT_name{{.*}}"CU1"
             ^
    <stdin>:26:32: note: scanning from here
    0x0000000b: DW_TAG_compile_unit
                                   ^
    <stdin>:29:2: note: possible intended match here
     DW_AT_name ()
     ^

BOLT uses MCAsmLayout to calculate the output values of basic blocks.
This means output values are calculated based on a pre-linking state and
any changes to symbol values during linking will cause incorrect values
to be used.

This issue was first addressed in D154604 by adding all basic block
symbols to the symbol table for the linker to resolve them. However, the
runtime overhead of handling this huge symbol table turned out to be
prohibitively large.

This patch solves the issue in a different way. First, a temporary
section containing [input address, output symbol] pairs is emitted to the
intermediary object file. The linker will resolve all these references
so we end up with a section of [input address, output address] pairs.
This section is then parsed and used to:
- Replace BinaryBasicBlock::OffsetTranslationTable
- Replace BinaryFunction::InputOffsetToAddressMap
- Update BinaryBasicBlock::OutputAddressRange

Note that the reason this i...

The `STGloop` family of pseudo-instructions all expand to a loop which
iterates over a region of memory setting all its MTE tags to a given
value. The loop writes to the flags in order to check termination. But
the unexpanded pseudo-instructions were not marked as modifying the
flags. Therefore it was possible for one to end up in a location where
the flags were live, and then the loop would corrupt them.

We spotted the effect of this in a libc++ test involving a lot of
complicated inlining, and haven't been able to construct a smaller
test case that demonstrates actual incorrect output code. So my test
here is just checking that `implicit-def $nzcv` shows up on the
pseudo-instructions as they're output from isel.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D158262

Which was done in https://reviews.llvm.org/D157058. This follows the fix
for lldb-server in https://reviews.llvm.org/D157589.

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D158391

83a06997 broke this test but
we only saw the failure on a subset of the flang bots because
it requires 3 target backends, and most of ours only enable AArch64.

Use %if to run as much of the test as we can with the targets
we have.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D158264

Differential Revision: https://reviews.llvm.org/D158309

The test clang/test/SemaCXX/template-64605.cpp uses pragma FENV_ACCESS,
which is not supported on all targets. Restrict it to x86_64 only.

When an expression is instantiated, TreeTransform skips ImplicitCastExpr
nodes, assuming they are recreated when the instantiated expression is
built. It breaks functions that use non-default floating-point options,
because they are kept in these ImplicitCastExprs. In this case the
recreated ImplicitCastExpr takes FP options from the current Sema state
and not from AST node.

To fix this issue the FP options in Sema object are set when a compound
statement is cloned in TreeTransform.

This change fixes https://github.com/llvm/llvm-project/issues/64605
([Regression 16 -> 17] Template instantiation ignores FENV_ACCESS being
ON for both definition and instantiation).

Differential Revision: https://reviews.llvm.org/D158158

When the 'int Four = Two;' is sunk into the 'case 0:' block,
the debug value for 'Three' is set incorrectly to 'poison'.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D158171

Binary and decimal values were reconginzed by strtoll, which returns
error when the msb is 1, and the error was ignored, resulting to wrong
results.

This patch fixes the issue.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D157079

This patch adds lowering support for threadprivate
variables encapsulated in a common block and
marked inside a copyin clause.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D157083