See #71911

Since the return value of this function is slightly more involved than
the void/bool/int/size_t return values we've seen so far, also refactor
this.

This used to just pass on the given parameter, but we need to respect
the given bit width.

Alive2: https://alive2.llvm.org/ce/z/F9HG3M

This missed optimization is discovered with the help of
https://github.com/AliveToolkit/alive2/pull/962.

Special-casing has been already removed.

`LIBCXXABI_SYSROOT`, `LIBCXXABI_TARGET_TRIPLE` and
`LIBCXXABI_GCC_TOOLCHAIN` are not supported anymore. Based on the
comment, the warning should be removed after branching for LLVM 15.

Reverts llvm/llvm-project#71861

This change implements the correct *level* sizes set up for the direct
IR codegen fields in the sparse storage scheme. This brings libgen and
codegen together again.

This is step 3 out of 3 to make sparse_tensor.new work for BSR

This should have been included in b2bbe8cc. Adding it should fix the bot
failures in https://lab.llvm.org/buildbot/#/builders/85/builds/20288

Align with the rest of the spirv dialect by using a functional type
syntax.

Regex for updating existing code:
`spirv\.VectorShuffle (\[.+\]) (%[^:]+): ([^,]+), (%[^:]+): ([^\s]+) ->(.+)`
 ==>
`spirv.VectorShuffle $1 $2, $4 : $3, $5 ->$6`

possible, NFC.

Example:

#CSR = #sparse_tensor.encoding<{
  map = (d0, d1) -> (d0 : dense, d1 : compressed),
}>

// CHECK: #[[$CSR.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0
: dense, d1 : compressed) }>
// CHECK-LABEL: func private @sparse_csr(
// CHECK-SAME: tensor<?x?xf32, **#[[$CSR]]**>)
func.func private @sparse_csr(tensor<?x?xf32, #CSR>)

Currently, the ConstructorKind member variable in AddressSanitizerPass
gets overriden by the ClConstructorKind whether the option is passed
from the command line or not. This override should only happen if the
ClConstructorKind argument is passed from the command line. Otherwise,
the constructor should honor the argument passed to it. This patch makes
this fix.

rdar://118423755

bitmask_enum.h is essentially a copy of llvm/ADT/BitmaskEnum.h, with some minor
cleanup and renaming.

The bit_ceil function is a placeholder for std::bit_ceil, which we can use once
compiler-rt can use c++20.

These utilities will be used to simplify bitfield enum usage in upcoming
ORC-RT patches.

This patch adds the following check from OpenMP 5.2.

```
If the directive has a clause, it must contain at least one enter clause
or at least one link clause.
```

Also added a warning for the deprication of `TO` clause on `DECLARE
TARGET` construct.

```
The clause-name to may be used as a synonym for the clause-name enter.
This use has been deprecated.
```

Based on the tests for to clause, the tests for enter clause are added.

This patch does not add tests where both to and enter clause are used together.

Fixed #62780.

@StephanTLavavej mentioned the libc++ tests no longer works for MSVC
STL. The regex changes have been provided by Stephan.

When setting conditional breakpoints, we currently assume that a call to
UserExpression::Parse() can be cached and resued multiple times. This
may not be true for every user expression. Add a new method so
subclasses of UserExpression can customize if they are parseable or not.

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani <sivan.shani@arm.com>

This reverts commit 186db1bc.

This relands commit 0718c1a8.

The REQUIRES flag in the test that was added only specified that the
machine needed to have the capability to execute the snippet rather than
actually run it with performance counters. This would work with
--dummy-perf-counters, but that is not currently supported in the
subprocess execution mode. So for now, we require the ability to
actually perform measurements to prevent test failures in configurations
that don't have libpfm or access to performance counters.

These error messages are written in a way that makes sense to an lldb
developer, but not to an end user who asks lldb to run on a compressed
corefile or whatever. Simplfy the messages.

Using a combination of reordering fields and using empty SubclassData32
/ SubclassData1, it's possible to improve the size of data structures
used to store debug info in the IR:

Before:

DILexicalBlock: 24
DILexicalBlockFile: 24
DIModule: 24
DITemplateParameter: 24
DICommonBlock: 24
DIMacro: 24
DICompileUnit: 56
DIType: 48
DINamespace: 24
DIVariable: 24
DIGlobalVariable: 32
DILocalVariable: 32
DILabel: 24

After:

DILexicalBlock: 24
DILexicalBlockFile: 16
DIModule: 16
DITemplateParameter: 16
DICommonBlock: 16
DIMacro: 16
DICompileUnit: 48
DIType: 40
DINamespace: 16
DIVariable: 24
DIGlobalVariable: 24
DILocalVariable: 32
DILabel: 16

[Driver,Gnu] Simplify -static -static-pie -shared -pie handling and suppress -shared -rdynamic warning

These options select different link modes (note: -shared -static can be
used together for musl and mingw). It makes sense to place them
together, which enables some simplification. The relevant ld options
are now consistently placed after -m, similar to GCC.

While here, suppress -Wunused-command-line-argument warning when -shared
-rdynamic are used together (introduced by commit
291f4a00). It can be argued either way
whether the warning is justified (in ELF linkers --export-dynamic
functionality is subsumed by -shared), but it is not useful (users can
do -Wl,--export-dynamic, bypassing the driver diagnostic).

[X86]: Enable custom lowering for fabs.v8f16 on AVX

Currently, custom lowering of fabs.v8f16 requires AVX512FP16, which is
too restrictive. For v8f16 fabs lowering, no instructions in AVX512FP16
are needed. Without the fix, horribly inefficient code is generated
without AVX512FP16. Note instcombiner generates calls to intrinsics
@llvm.fabs.v8f16 when simplifyping AND <8 x half> operations.

Test coverage for an upcoming set of changes