This commit implements layout_right in support of C++23 mdspan
(https://wg21.link/p0009

). layout_right is a layout mapping policy
whose index mapping corresponds to the memory layout of multidimensional
C-arrays, and is thus also referred to as the C-layout.

Co-authored-by: Damien L-G <dalg24@gmail.com>

Differential Revision: https://reviews.llvm.org/D151267

D120936 has made the loss of `__unaligned` qualifier NOT a bad-conversion.
Because of this, the bad-conversion note about the loss of this qualifier does not take effect.
e.g.
```
void foo(int *ptr);

void func(const __unaligned int *var) { foo(var); }
```
BEFORE this patch:
```
source.cpp:3:41: error: no matching function for call to 'foo'
    3 | void func(const __unaligned int *var) { foo(var); }
      |                                         ^~~
source.cpp:1:6: note: candidate function not viable: 1st argument ('const __unaligned int *') would lose __unaligned qualifier
    1 | void foo(int *ptr);
      |      ^
    2 |
    3 | void func(const __unaligned int *var) { foo(var); }
      |                                             ~~~
```
AFTER this patch:
```
source.cpp:3:41: error: no matching function for call to 'foo'
    3 | void func(const __unaligned int *var) { foo(var); }
      |                                         ^~~
source.cpp:1:6: note: candidate function not viable: 1st argument ('const __unaligned int *') would lose const qualifier
    1 | void foo(int *ptr);
      |      ^
    2 |
    3 | void func(const __unaligned int *var) { foo(var); }
      |                                             ~~~
```
Please note the different mentions of `__unaligned` and `const` in notes.

Reviewed By: cjdb, rnk
Differential Revision: https://reviews.llvm.org/D153690

The initial implementation of the modernize-use-std-print check was
capable of converting calls to printf (etc.) which used the return value
to calls to std::print which has no return value, thus breaking the
code.

Use code inspired by the implementation of bugprone-unused-return-value
check to ignore cases where the return value is used. Add appropriate
lit test cases and documentation.

Reviewed By: PiotrZSL

Differential Revision: https://reviews.llvm.org/D153860

DWARFLinker has a compatibility feature with dsymutil-classic.
It may keep location expression attribute even if does not
reference live address. Current llvm-dwarfdump --verify
reports a error if variable references an address but is not
added into the .debug_names table.

error: Name Index @ 0x0: Entry for DIE @ 0xf35 (DW_TAG_variable) with name seed missing.

DW_TAG_variable
  DW_AT_name      ("seed")
  DW_AT_type      (0x00000000000047b7 "uint64_t")
  DW_AT_location  (DW_OP_addr 0x9ff8)  <<<< dead address

DWARFLinker does not add the variable into .debug_names table
because it references dead address. To have a valid variable and
consistent accelerator table it is necessary to remove location expression
referencing dead address. This patch removes dsymutil-classic
compatibilty feature.

Differential Revision: https://reviews.llvm.org/D153988

Revert D152502 and instead optimize away copy from undefs, but clear the undef flag on the original copy.
Apparently, not optimizing the COPY can cause performance issues in some cases.

Fixes SWDEV-405813, SWDEV-405899

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153838

Add support for performing a link step on z/OS.  This will support C & C++ building executables and shared libs.

Reviewed By: zibi, abhina.sreeskantharajan

Differential Revision: https://reviews.llvm.org/D153580

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D149168

 Sometimes PHI have different incoming values, such as:
 ```
%1:vgpr_256 = COPY %0:agpr_256
%2:vgpr_32 = COPY %1:vgpr_256.sub0
```

Those weren't handled, which could lead to massive performance issues if break-large-PHIs kicked in + AGPRs were used (MFMA)

Fixes SWDEV-407986

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D153879

Currently getGEPCost uses the target type of the GEP as a heuristic for
the type that will be accessed, to pass onto isLegalAddressingMode.
Targets use this to work out if a GEP can then be folded into the
load/store instruction that uses the GEP.
For example, on RISC-V loads and stores can have an offset added to a
base register folded into a single instruction, so the following GEP is
free:

%p = getelementptr i32, ptr %base, i32 42       ; getInstructionCost = 0
%x = load i32, ptr %p                           ; getInstructionCost = 1
------------------------------------------------------------------------
lw t0, a0(42)

However vector loads and stores cannot have an offset folded into them,
so the following GEP is costed:

%p = getelementptr <2 x i32>, ptr %base, i32 42 ; getInstructionCost = 1
%x = load <2 x i32>, ptr %p                     ; getInstructionCost = 1
------------------------------------------------------------------------
addi  a0, 42
vle32 v8, (a0)

The issue arises whenever there is a mismatch between the target type of
the GEP and the type that is actually accessed:

%p = getelementptr i32, ptr %base, i32 42       ; getInstructionCost = 0
%x = load <2 x i32>, ptr %p                     ; getInstructionCost = 1
------------------------------------------------------------------------
addi  a0, 42
vle32 v8, (a0)

Even though this GEP will result in an add instruction, because TTI
thinks it's loading an i32, it will think it can be folded and not
charge for it.

The target type can become mismatched with the memory access during
transformations, noticeably during SLP where a scalar base pointer will
be reused to perform a vector load or store.

This patch adds an optional AccessType argument to getGEPCost which
allows the type of memory accessed by users to be passed in as a hint,
so that we can more accurately determine if the GEP can be folded into
its users.

If AccessType is not provided, getGEPCost falls back to the old
behaviour of using the PointeeType to guess the memory access type. This
can be revisited in a later patch.

Also for now, only GEPs with exactly one user use the access type hint.
Whilst we could look through all users and use all access types to
determine if we can fold the GEP, this patch avoids doing so to prevent
O(N) behaviour.

Differential Revision: https://reviews.llvm.org/D149889

This patch updates the tests in gep.ll to have explicitly memory
accesses using them, to illustrate the new behaviour in D149889.
New tests have also been added for mismatched pointer types and memory
access types, and gep-zero-indices.ll has also been added to make sure
that we always cost GEPs with all zero indices as free.

Add `ViewLikeOpInterface` to `ExtractStridedMetadataOp` as it returns its buffer as one of the results.
Add mem Read/Write attributes to atomic ops.

Differential Revision: https://reviews.llvm.org/D153647

See D153611. Tests for the cost of icmp(and, 0) are added, in addition to
expanding the extractelements-to-shuffle.ll test, which has always been a bit
simple, to include a more complete example with both a vector and scalar
version. The icmp(and, 0) costs are targetting at improving the second when the
cost of vector inserts and extracts is lowered.

The existing code assumes that both `DeclareRISCVVBuiltins` and
`DeclareRISCVSiFiveVectorBuiltins` are set when coming into the if-statement
under SemaLookup.cpp.

This is not the case and causes issue #63571.

This patch resolves the issue.

Reviewed By: 4vtomat, kito-cheng

Differential Revision: https://reviews.llvm.org/D154050

Fixes https://github.com/llvm/llvm-project/issues/63223

Differential Revision: https://reviews.llvm.org/D153560

These tests will be optimized with BSETI32/BCLRI32
in the future.

Reviewed By: zixuan-wu

Differential Revision: https://reviews.llvm.org/D153613

Reviewed By: zixuan-wu

Differential Revision: https://reviews.llvm.org/D153402

Differential Revision: https://reviews.llvm.org/D153978

This patch adds a softmax op.
For now, nothing interesting happens, we can only do a round trip.
Later patches will add the tiling interface and the lowering of this op to
a sequence of simpler ops.

This is graduating the linag_ext.softmax op from iree to LLVM.

Original implementation from Harsh Menon <harsh@nod-labs.com>
Nicolas Vasilache <nicolas.vasilache@gmail.com> co-authored this patch.

Differential Revision: https://reviews.llvm.org/D153422

[mlir][GreedyPatternRewriter] Add out param to detect changes in IR in `applyPatternsAndFoldGreedily`

This allows users of `applyPatternsAndFoldGreedily` to detect if any MLIR changes have occurred. An example use-case is where we expect the `applyPatternsAndFoldGreedily` to change the IR and want to validate that it indeed does change it.

Differential Revision: https://reviews.llvm.org/D153986

Extra tests for D152730.

This addresses the trivial cases that only require removing the
operand classes and renaming related entities.

Part of <https://github.com/llvm/llvm-project/issues/62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D153965

This reverts commit 57e09316.

/Users/jiefu/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:97:33: error: unused variable 'FuncInfo' [-Werror,-Wunused-variable]
      RISCVMachineFunctionInfo *FuncInfo =
                                ^
/Users/jiefu/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:106:29: error: unused variable 'TLI' [-Werror,-Wunused-variable]
      const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
                            ^
2 errors generated

There is an issue: https://github.com/llvm/llvm-project/issues/63515
The issue is because when expanding SPLAT_VECTOR_SPLIT_I64_VL node, only memoperand is used to create dependency.
However in ScheduleDAGNodes, dependency is checked with chain only, and breaks order of store/load instructions.
I think in llvm.bitreverse.nxv2i64 intrinsic SPLAT_VECTOR_SPLIT_I64_VL nodes are parallel processed,
so no chain should be add to these nodes.
Using temporary in expanding SPLAT_VECTOR_SPLIT_I64_VL node can keep vlse instruction get correct value
no matter order of store instructions is changed.

Differential Revision: https://reviews.llvm.org/D153743

Extra tests for D152730.

This reverts commit 3254623d.

One test has been updated to add the "-s" flag which along with
86fd957a should fix the tests on MacOS.

An assert on hijack listener added in that patch was removed, it seems
to be correct on MacOS but not on Linux.

Test from D153392 in both the alloca and malloc variants.

Delegate checking of the constraint & its preconditions to the existing
::isValid. This reduces duplication and allows additional optimizations
together with D152730.

Debug intrinsics are allowed to violate SSA dominance and might thus
cause the LLVM import to produce invalid LLVM dialect. This commit
ensures that the debug intrinsics are emitted right after the definition
of their SSA operands.
As the position of debug intrinsics has no meaning, changing it has no
semantic implication.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D153984

The error could be awkward to work around when experimenting with flags
that didn't have a matching multilib. It also broke many tests when
multilib.yaml was present in the build directory.

Reviewed By: simon_tatham, MaskRay

Differential Revision: https://reviews.llvm.org/D153885

Also replace aarch64_be-*-eabi with aarch64_be

Using "eabi" for aarch64 targets is a common mistake and warned by Clang Driver.
We want to avoid it elsewhere as well. Just use the common "aarch64" without
other triple components.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D153943

Before this patch, the compiler gave a bump to the inline-threshold
when the total size of the allocas passed as arguments to the
callee was below 256 bytes.
This heuristic ignores that some of these allocas could have be removed
by SROA if inlining was applied.

Ideally, this bonus would be attributed to the threshold once the
size of all the allocas that could not be handled by SROA is known:
at the end of the InlineCost analysis.
However, we may never reach this point if the inline-cost analysis exits
early when the inline cost goes over the threshold mid-analysis.

This patch proposes:
* Attribute the bonus in the inline-threshold when allocas are passed
  as arguments (regardless of their total size).
* Assigns a cost to each alloca proportional to its size,
  such that the cost of all the allocas cancels the bonus.

Potential problems:
* This patch assumes that removing alloca instructions with SROA is
  always profitable. This may not be the case if the total size of the
  allocas is still too big to be promoted to registers/LDS.
* Redundant calls to getTotalAllocaSize
* Awkwardly, the threshold attributed contributes to the single-bb and
  vector bonus.

Reviewed By: scchan

Differential Revision: https://reviews.llvm.org/D149741

On AMDGPU, alloca instructions have penalty that can
be avoided when SROA is applied after inlining.

This patch introduces the default implementation of
TargetTransformInfo::getCallerAllocaCost.

Reviewed By: mtrofin

Differential Revision: https://reviews.llvm.org/D149740

Add flags allowing to use compile flags and libraries provided in cache with libunwind.
Similar flags are already present in libc++ and libc++abi CMakeLists files.

Differential Revision: https://reviews.llvm.org/D150252

[RISCV] Do a more complete job of disabling extending loads and truncating stores for fixed vector types.

We weren't marking some combinations as Expand if ones of the
types wasn't legal.

Fixes #63596.

Strengthen the fold for icmps of non-overlapping storage, by
working on the difference of offsets, rather than considering
both offsets independently. In particular, this allows handling
comparisons of pointers to the end of equal-sized allocations.

Proofs: https://alive2.llvm.org/ce/z/Po2nL4

Differential Revision: https://reviews.llvm.org/D153752

The newly added tests crash without the other changes in this patch.

Reviewed By: sammccall, xazax.hun, gribozavr2

Differential Revision: https://reviews.llvm.org/D153960