We had some uses of uint64_t and unsigned. These all come from tblgen
code that is templated on InsnType which is currently uint32_t.

Summary:
All of these are functionally the same code, just compiled for separate
architectures. We currently do not expose a way to execute these on
separate architectures as the host plugin works using `dlopen` into the
same process, and therefore cannot possibly be an incompatible
architecture. (This could work with a remote plugin, but this is not
supported yet).

This patch simply renames all of these to the same thing so we no longer
need to check around for its varying definitions.

Resolves #89674

Before deleting extractelement instruction for vectorized GEP with
external users, need to check that all users vectorized before deleting
this extractelement.

These are now close enough that they can be swapped out.

Certain C++ types, such as `std::chrono::tzdb` in libstdc++, are
non-copyable, but don't explicitly delete their copy constructor.
Instead, they trigger template instantiation errors when trying to call
their implicit copy constructor. The Swift compiler inserts implicit
copies of value types in some cases, which trigger compiler errors for
such types.

This adds a Clang API Notes attribute that allows annotating C++ types
as non-copyable in Swift. This lets the Swift compiler know that it
should not try to instantiate the implicit copy constructor for a C++
struct.

rdar://127049438

This prints the opcode bytes in the same order as GNU objdump without a
space between them.

In some cases, MSVC's mangling for arm64ec thunks includes the alignment
of a struct. I added some code to try to match... but it never really
worked right. The issues:

- Alignment is only mangled if it's 16 or more (I guess the default is
supposed to be 8).
- Alignment isn't mangled on return values (since the memory is
allocated by the caller).

The current patch leaves hooks to make alignment mangling work... but
doesn't actually ever mangle alignment: clang never actually encodes a
relevant alignment into the IR. Once we get clang to emit the real
size/alignment of structs, we can start emitting it.

Strides are used through a sext/zext and the known constant value (1)
isn't propagated during codegen.

Previously we had an individiaul global array of implied extensions for
each extension that needed it. This allowed each array to have a
different length. Then we had a sorted table that stored pointers and
size for the indivual arrays keyed by the extension name.

This patch changes the sorted table to use multiple rows if multiple
extensions are implied. We use equal_range instead of lower_bound to
find all the rows that apply to a given extension.

The CombineIntoExts array was also modified to store only the extension
name that need to be combined. This extension name is looked up in the
implied table to find all the extensions it depends on.

This patch changes to use system call `syssmt()` instead of
`lpar_get_info()` to get the number of SMTs (logical processors) per
physical processor for AIX. `lpar_get_info()` gives the max number of
SMTs that the physical processor can support while `syssmt()` returns
the number that is currently configured.

LeafChildren is used in an earlier version of the SuffixTree
implementation to keep track of each nodes' leaf nodes. In the
new/current version, this variable is no longer used, but a comment is
left behind. This patch updates the comment.

This was omitted in c1086532 and not detected by the CI since
clang-tidy is not running. This fixes the exports.

Fixes: https://github.com/llvm/llvm-project/issues/89898

Allow to fold BSL/EOR instuctions to NBSL instruction for scalable
vectors.

These macros are used by STL implementations to support implementation
of std::hardware_destructive_interference_size and
std::hardware_constructive_interference_size

Fixes #60174

---------

Co-authored-by: Louis Dionne <ldionne.2@gmail.com>

Temporary symbols generated for .eh_frame and .debug_line have an empty
name, which appear in .symtab in the presence of RISC-V style linker
relaxation and will not be discarded by ld/objcopy --discard-locals
(-X).

In contrast, GNU assembler's riscv port assigns a fake name ".L0 " (with
a trailing space) to these symbols so that will be discarded by
ld/objcopy --discard-locals.

This patch matches the GNU behavior. Since Clang's RISC-V targets pass
-X to ld, and GNU ld defaults to -X for RISC-V targets, these ".L0 "
symbols will be discarded after linking by default, as expected by
users.

The llvm-symbolizer special case for RISC-V `SF_FormatSpecific` symbols
https://reviews.llvm.org/D98669 needs to be adjusted.

Note: `"":` in assembly currently crashes.

Note: bolt tests used /usr/bin/clang before
llvmorg-19-init-9532-g59bfc310.
The revert llvmorg-19-init-9531-g28b55342 actually broke
bolt/test/RISCV/fake-label-no-entry.c

This PR adds support for `memref.collapse_shape` to sub-byte type emulation. The `memref.collapse_shape` becomes a no-opt given that we are flattening the memref as part of the emulation (i.e., we are collapsing all the dimensions).

In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70:
/llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:8:48: error: 'cast' is deprecated: Use mlir::cast<U>() instead [-Werror,-Wdeprecated-declarations]
      VectorType vt = op.getResult().getType().cast<VectorType>();
                                               ^
/llvm-project/mlir/include/mlir/IR/Types.h:345:9: note: 'cast' has been explicitly marked deprecated here
U Type::cast() const {
        ^
In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70:
/llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:8:48: error: 'cast<mlir::VectorType>' is deprecated: Use mlir::cast<U>() instead [-Werror,-Wdeprecated-declarations]
      VectorType vt = op.getResult().getType().cast<VectorType>();
                                               ^
/llvm-project/mlir/include/mlir/IR/Types.h:112:5: note: 'cast<mlir::VectorType>' has been explicitly marked deprecated here
  [[deprecated("Use mlir::cast<U>() instead")]]
    ^
In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70:
/llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:32:48: error: 'cast' is deprecated: Use mlir::cast<U>() instead [-Werror,-Wdeprecated-declarations]
      VectorType vt = op.getResult().getType().cast<VectorType>();
                                               ^
/llvm-project/mlir/include/mlir/IR/Types.h:345:9: note: 'cast' has been explicitly marked deprecated here
U Type::cast() const {
        ^
In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70:
/llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:32:48: error: 'cast<mlir::VectorType>' is deprecated: Use mlir::cast<U>() instead [-Werror,-Wdeprecated-declarations]
      VectorType vt = op.getResult().getType().cast<VectorType>();
                                               ^
/llvm-project/mlir/include/mlir/IR/Types.h:112:5: note: 'cast<mlir::VectorType>' has been explicitly marked deprecated here
  [[deprecated("Use mlir::cast<U>() instead")]]
    ^
4 errors generated.

It seems that the description of the SEI CERT rules was moved from
`www.securecoding.cert.org` to `wiki.sei.cmu.edu` and the page IDs were
not preserved during the transition.

However, the old domain name redirects to the new one and permalinks
derived from the name of the rule still work, so I kept using the old
domain name to be consistent with other documentation files using it.

This pull request implements LWG3984: ranges::to's recursion branch
may be ill-formed.

In the current implementation, ranges::to's recursion branch pipes the
range into a `views::transform(/* lambda */)`, which is a __range_adaptor_closure
object. In libc++, the pipe operator of __range_adaptor_closure requires a
viewable_range, so the following code won't compile, as the type of lvalue
`r` doesn't model viewable_range:

  #include <ranges>
  #include <vector>
  #include <list>

  int main() {
    std::vector<std::vector<int>> v;
    auto r = std::views::all(std::move(v));
    auto l = std::ranges::to<std::list<std::list<int>>>(r);
  }

Co-authored-by: A. Jiang <de34@live.cn>

This patch adds test for
[CWG2149](https://cplusplus.github.io/CWG/issues/2149.html), following
[P3106R1](https://wg21.link/p3106R1) "Clarifying rules for brace elision
in aggregate initialization" and a clarification note on top of it added
on April 2024.

I haven't found a better way to check for equality of values inside
array in 98 mode than to dump AST. I'm open to suggestions there.

See https://mlir.llvm.org/deprecation and
https://discourse.llvm.org/t/preferred-casting-style-going-forward.

This PR adds a new pattern to the set of patterns used to resolve the offset, sizes and
stride of a memref. Similar to `ExtractStridedMetadataOpSubviewFolder`, the new
pattern resolves strided_metadata(collapse_shape) directly, without introduce a
reshape_cast op.

We can try to vectorize long store sequences, if short ones were
unsuccessful because of the non-profitable vectorization. It should not
increase compile time significantly (stores are sorted already,
complexity is n x log n), but vectorize extra code.

Metric: size..text

Program                                                                         size..text
                                                                                results     results0    diff
         test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test  1088012.00  1088236.00  0.0%
                  test-suite :: SingleSource/UnitTests/matrix-types-spec.test   480396.00   480476.00  0.0%
          test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test   664613.00   664661.00  0.0%
         test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test   664613.00   664661.00  0.0%
        test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test  2041105.00  2040961.00 -0.0%
                 test-suite :: MultiSource/Applications/JM/lencod/lencod.test   836563.00   836387.00 -0.0%
                 test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test  1035100.00  1032140.00 -0.3%

In all benchmarks extra code gets vectorized

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/88563

This reverts commit 6578356a.

The patch had no effect due to a silly mistake and fixing the mistake
causes other problems.

Summary:
This call was removed a few months ago to allow the runtime to actually
init / deinit in a correct order. However that patch forgot to remove a
few leftover uses.

It's really unfortunate that STORE and ATOMIC_STORE are separate
opcodes. This duplicates a basic simplify demanded for the truncating
case. This avoids some AMDGPU lit regressions in a future patch.

I'm not sure how to craft a test that exposes this without first
introducing the regressions by promoting half to i16.

A recent patch changed the array sections to work differently for
OpenACC, including for the diagnostic, so the FIXME is now irrelevant.

[DAG] visitORCommutative - fold build_pair(not(x),not(y)) -> not(build_pair(x,y)) style patterns (#90050)

(Sorry, not an actual build_pair node just a similar pattern).

For cases where we're concatenating 2 integers into a double width integer, see if both integer sources are NOT patterns.

We could take this further and handle all logic ops with a constant operands, but I just wanted to handle the case reported on #89533 initially.

Fixes #89533

The reference to a particular page number is long since out of date.
Instead, let's name the section title which at least has remained stable
so far.

When cloning instructions from one basic block to another,
the debug values are not remapped, in the same was as the
normal instructions.

Add support for the moveq instruction, which is both faster and smaller
(1/2 to 1/3 the size) than a move with immediate to register.

This change introduces the instruction, along with a set of
pseudoinstructions to handle immediate moves to a register that is
lowered post-RA.

Pseudos are used as moveq can only write to the full register, which
makes
matching i8 and i16 immediate loads difficult in tablegen. Furthermore,
selecting moveq before RA constrains that immediate to be moved into a
data
register, which may not be optimal.

The bulk of this change are fixes to existing tests, which cover the new
functionality sufficiently.

Adding reproducers for github issues #84653 and #85190.

Caught by compiling a project (SerenityOS) that uses compiler-rt and not
silencing warnings from system headers.

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/

Avoid turning a BUILD_VECTOR that can be recognized as "all zeros",
"all ones" or "constant" into something that depends on
freeze(undef), as that would destroy those properties.

Instead we replace undef by 0/-1 in such vectors, making it possible
to fold away the freeze. We typically use -1 if the BUILD_VECTOR
would identify as "all ones", and otherwise we use the value 0.