1. Dec 05, 2023
    • Kamau Bridgeman's avatar
      XFailing test cases that fail on PowerPC · 503dbe75
      Kamau Bridgeman authored
      These test cases fail when the libcxx and libcxxabi runtimes are
      built on Linux PowerPC. XFailing them until the issue is resolved.
      503dbe75
    • Tobias Gysi's avatar
      [mlir][llvm] Fix attribute printer warning (NFC)(#74351) · 78580715
      Tobias Gysi authored
      This commit fixes a compilation warning caused by the printExpressionArg
      function that previously returned LogicalResult instead of void.
      
      The warning has been introduced by #73367.
      78580715
    • Durga's avatar
      [MLIR][NVVM]: Add cp.async.mbarrier.arrive Op (#74241) · f81eb7da
      Durga authored
      
      
      Add:
      * an Op for 'cp.async.mbarrier.arrive', targeting the
      nvvm_cp_async_mbarrier_arrive* family of intrinsics.
      * The 'noinc' intrinsic property is modelled as a default-valued-attr of
      type I1.
      * Test cases are added to verify the Op as well as the intrinsic
      lowering.
      
      Signed-off-by: default avatarDurgadoss R <durgadossr@nvidia.com>
      f81eb7da
    • vdonaldson's avatar
      [flang] IEEE_ARITHMETIC and IEEE_EXCEPTIONS intrinsic module procedures (#74138) · 3aba9264
      vdonaldson authored
      Implement a selection of intrinsic module procedures that involve
      exceptions.
      
       - IEEE_GET_FLAG
       - IEEE_GET_HALTING_MODE
       - IEEE_GET_MODES
       - IEEE_GET_STATUS
       - IEEE_LOGB
       - [f23] IEEE_MAX, IEEE_MAX_MAG, IEEE_MAX_NUM, IEEE_MAX_NUM_MAG
       - [f23] IEEE_MIN, IEEE_MIN_MAG, IEEE_MIN_NUM, IEEE_MIN_NUM_MAG
       - IEEE_QUIET_EQ, IEEE_QUIET_GE, IEEE_QUIET_GT,
       - IEEE_QUIET_LE, IEEE_QUIET_LT, IEEE_QUIET_NE
       - IEEE_SET_FLAG
       - IEEE_SET_HALTING_MODE
       - IEEE_SET_MODES
       - IEEE_SET_STATUS
       - IEEE_SIGNALING_EQ, IEEE_SIGNALING_GE, IEEE_SIGNALING_GT,
       - IEEE_SIGNALING_LE, IEEE_SIGNALING_LT, IEEE_SIGNALING_NE
       - IEEE_SUPPORT_FLAG
       - IEEE_SUPPORT_HALTING
      3aba9264
    • Natalie Chouinard's avatar
      [SPIR-V] Add SPIRV-Tools for testing (#73044) · f368e642
      Natalie Chouinard authored
      Add spirv-dis (disassembler) and spirv-val (validator) from SPIRV-Tools
      as external dependencies for testing the SPIR-V backend. These tools are
      test dependencies only.
      
      SPIR-V backend tests now have a dependency on the spirv-dis and
      spirv-val targets when the `LLVM_INCLUDE_SPIRV_TOOLS_TESTS` cmake
      variable is set, which allows additional test files with the `REQUIRES:
      spirv-tools` constraint to run, along with additional `RUN: %if
      spirv-tools ...` lines in existing tests. All other SPIR-V backend tests
      will run normally when `LLVM_INCLUDE_SPIRV_TOOLS_TESTS` is not set.
      
      Several tests are included to show these tools' use, however more tests
      will be migrated and added later.
      * OpVariable_order.ll shows how spirv-val can catch bugs in the backend.
      * basic_int_types_spirvdis.ll shows how tests can be much shorter and
      more readable by FileChecking the spirv-dis output.
      * basic_int_types.ll shows how an additional RUN line can add validation
      to existing tests.
      
      RFC:
      https://discourse.llvm.org/t/rfc-add-a-test-dependency-on-spirv-tools/75135
      f368e642
    • Boian Petkantchin's avatar
      [mlir][mesh] Add TableGen deffinitions of more collective ops (#73842) · dff2f59b
      Boian Petkantchin authored
      Add definitions for
      broadcast, gather, receive, reduce, scatter, send and shift.
      dff2f59b
    • Benjamin Maxwell's avatar
      [mlir][ArmSME] Remove ArmSMETypeConverter (and configure LLVM one instead) (#73639) · 01e40a8a
      Benjamin Maxwell authored
      This patch removes the ArmSMETypeConverter, and instead updates
      `populateArmSMEToLLVMConversionPatterns()` to add an ArmSME vector type
      conversion to the existing LLVMTypeConverter. This makes it easier to
      add these patterns to an existing `-to-llvm` lowering pass.
      01e40a8a
    • Andrzej Warzyński's avatar
      [mlir][vector] Make `TransposeOpLowering` configurable (#73915) · bbd2b08b
      Andrzej Warzyński authored
      Following the discussion here:
      
        * https://github.com/llvm/llvm-project/pull/72105
      
      this patch makes the `TransposeOpLowering` configurable so that one can select
      whether to favour `vector.shape_cast` over `vector.transpose`.
      
      As per the discussion in #72105, using `vector.shape_cast` is very beneficial
      and desirable when targeting `LLVM IR` (CPU lowering), but won't work when
      targeting `SPIR-V` today (GPU lowering). Hence the need for a mechanism to be
      able to disable/enable the pattern introduced in #72105. This patch proposes one
      such mechanism.
      
      While this should solve the problem that we are facing today, it's understood to
      be a temporary workaround. It should be removed once support for lowering
      `vector.shape_cast` to SPIR-V is added. Also, (once implemented) the following
      proposal might make this workaround redundant:
      
        * https://discourse.llvm.org/t/improving-handling-of-unit-dimensions-in-the-vector-dialect/
      bbd2b08b
    • Brad Smith's avatar
      [flang] Remove GCC 7.2 workarounds (#73574) · 74e59e77
      Brad Smith authored
      The minimum GCC version was bumped from 7.1 to 7.4 so garbage collect
      the 7.2 workarounds.
      
      https://reviews.llvm.org/D156286
      74e59e77
    • Benjamin Kramer's avatar
      b935f1a7
    • Benjamin Kramer's avatar
      Remove unused includes. NFC. · 86accd4e
      Benjamin Kramer authored
      86accd4e
    • Thomas Schenker's avatar
      [clang-tidy] readability-container-contains literal suffixes (#74215) · 8ac84a95
      Thomas Schenker authored
      Before this PR, readability-container-contains fix-its did not handle
      integer literal suffixes correctly. It e.g. changed
      ```
        MyMap.count(2) != 0U;
      ```
      into
      ```
        MyMap.contains(2)U;
      ```
      
      With this PR, it correctly changes it to
      ```
        MyMap.contains(2);
      ```
      8ac84a95
    • DonatNagyE's avatar
      [analyzer] Let the checkers query upper and lower bounds on symbols (#74141) · 67f387c6
      DonatNagyE authored
      This commit extends the class `SValBuilder` with the methods
      `getMinValue()` and `getMaxValue()` to that work like
      `SValBuilder::getKnownValue()` but return the minimal/maximal possible
      value the `SVal` is not perfectly constrained.
      
      This extension of the ConstraintManager API is discussed at:
      https://discourse.llvm.org/t/expose-the-inferred-range-information-in-warning-messages/75192
      
      As a simple proof-of-concept application of this new API, this commit
      extends a message from `core.BitwiseShift` with some range information
      that reports the assumptions of the analyzer.
      
      My main motivation for adding these methods is that I'll also want to
      use them in `ArrayBoundCheckerV2` to make the error messages less
      awkward, but I'm starting with this simpler and less important usecase
      because I want to avoid merge conflicts with my other commit
      https://github.com/llvm/llvm-project/pull/72107 which is currently under
      review.
      
      The testcase `too_large_right_operand_compound()` shows a situation
      where querying the range information does not work (and the extra
      information is not added to the error message). This also affects the
      debug utility `clang_analyzer_value()`, so the problem isn't in the
      fresh code. I'll do some investigations to resolve this, but I think
      that this commit is a step forward even with this limitation.
      67f387c6
    • Momchil Velikov's avatar
    • Nick Desaulniers's avatar
      [TargetInstrInfo] update INLINEASM memoperands once (#74135) · ec000a65
      Nick Desaulniers authored
      In commit b0533598 ("[X86InstrInfo] support memfold on spillable
      inline asm
      (#70832)"), I had a last minute fix to update the memoperands. I
      originally
      did this in the parent foldInlineAsmMemOperand call, updated the mir
      test via
      update_mir_test_checks.py, but then decided to move it to the child call
      of
      foldInlineAsmMemOperand.
      
      But I forgot to rerun update_mir_test_checks.py. That last minute change
      caused
      the same memoperand to be added twice when recursion occurred (for tied
      operands). I happened to get lucky that trailing content omitted from
      the
      CHECK line doesn't result in test failure.
      
      But rerunning update_mir_test_checks.py on the mir test added in that
      commit
      produces updated output. This is resulting in updates to the test that:
      1. conflate additions to the test in child commits with simply updating
      the
         test as it should have been when first committed.
      2. look wrong because the same memoperand is specified twice (we don't
         deduplicate memoperands when added). Example:
      
      INLINEASM ... :: (load (s32) from %stack.0) (load (s32) from %stack.0)
      
      Fix the bug, so that in child commits, we don't have additional
      unrelated test
      changes (which would be wrong anyways) from simply running
      update_mir_test_checks.py.
      
      Link: #20571
      ec000a65
    • Da-Viper's avatar
      Fix #41439: Update the documentation with the correct information. (#69377) · 47a40e80
      Da-Viper authored
      Fixes #41439
      
      The documentation is update to say it is allowed to have omitted
      parameter names if the variable is not used
      47a40e80
    • Ulrich Weigand's avatar
      [SystemZ] Handle index-only addresses in (dis)assembler · 901e484f
      Ulrich Weigand authored
      Most addresses in SystemZ instructions take two registers,
      an index register and a base register.  However, either of
      those can be omitted.  If there is just a single register,
      this usually is taken as the base register - however, there
      are certain rare cases where you specifically want to use
      an index register but no base register.  This is currently
      not handled consistently by the assembler / disassembler.
      
      Fix this by
       - always emitting a dummy 0 as base register for index-
         only addresses
       - correctly handle dummy 0 as indicating no base register
         when parsing an address
      
      This is compatible with current GNU binutils behavior.
      901e484f
    • Ulrich Weigand's avatar
      [SystemZ] Fix __builtin_s390_vceq* inconsistency · 9d271392
      Ulrich Weigand authored
      The __builtin_s390_vceq* family of builtins currently take
      signed arguments with clang, but unsigned with GCC.  Update
      clang to match existing GCC precendent.
      9d271392
  2. Dec 04, 2023